Offset: systematic and random

Measure an OTA's input offset in a unity-gain buffer, explain the part that is in the schematic, and refer a mismatch in any transistor to the input.

Lesson: E5.4
Time: 25 min
Runs on: ngspice
Check: 5 questions

A temperature sensor read 2 °C high on every board: about 2 mV of input offset in its amplifier, multiplied by the gain after it. Part of the offset was in the schematic, and the rest came from transistors drawn identical that were not.

DC sweepA buffer's error, drawn identical and with 1 mV of mismatchThe error v_out − v_in of OTA-A as a unity-gain buffer, with identical devices and with M2's threshold 1 mV lower.

drawn identical
1 mV at M2

Input 900 mVdrawn identical = -2.166 mV · 1 mV at M2 = -3.159 mV
At 0.9 V the buffer with identical devices is 2.17 mV low. One millivolt of mismatch in M2 takes it to 3.16 mV.

Read the plot as a table

Input	drawn identical	1 mV at M2
600 mV	982.8 µV	-9.624 µV
700 mV	-280.3 µV	-1.273 mV
800 mV	-1.279 mV	-2.272 mV
900 mV	-2.166 mV	-3.159 mV
1 V	-3.114 mV	-4.106 mV
1.1 V	-4.277 mV	-5.269 mV
1.2 V	-6.221 mV	-7.213 mV

Measured on ngspice 42 (the lab netlist, 651 points).

A simulation that checks only the gain shows neither part.

What offset is and how to measure it

The input offset V_os of an amplifier is the differential input needed to put its output where the design wants it. Model it as a small voltage source in series with one input of an otherwise perfect amplifier. Any circuit around the amplifier then amplifies that source like a signal.

Measure it in a unity-gain buffer: the output drives the − input, and V_os = V_out − V_in. OTA-A (E5.3) at 0.9 V gives −2.17 mV. The loop has done the work of finding the input difference that balances the circuit.

Inputs tied, loop open

* both gates on the same 0.9 V
XT in in ot vdd otam

open_loop = 6.181800e-01: the output lands near node x, 282 mV below the input. Open loop, every microvolt is multiplied by the gain, so this says little about the offset.

Unity-gain buffer

* the output drives the - input
X0 in o0 o0 vdd otam

vos = -2.165886e-03: the buffer reports the offset itself.

Both in the lab netlist on ngspice 42.

Two kinds of offset add up. Systematic offset is in the schematic: it is the same on every chip, and the designer can remove it. Random offset comes from mismatch, the small random difference between transistors drawn the same, and it differs from chip to chip.

Systematic offset from unequal drain voltages

In OTA-A the diode node x sits at 0.618 V and the output at 0.898 V. So M3 and M4 have different source-drain voltages, and so do M1 and M2. Through channel-length modulation (E2.4), unequal voltages mean unequal currents: M3 carries 9.373 µA and M4 9.299 µA, with every device drawn perfect.

The loop cancels that imbalance with a small input difference. A first estimate: the drain voltage gap divided by the gain, V_os ≈ −(V_out − V_x)/A₀ = −0.280 V/137.1 = −2.04 mV, with A₀ = g_m2/(g_ds2 + g_ds4) from the operating point. The run gives −2.17 mV.

DC sweepThe offset vanishes where the drains matchAbove: the buffer's error. Below: the gap between the output and node x.

v(out) − v(in)
v(out) − v(x)

Input 675.1 mVv(out) − v(in) = -33.11 pV · v(out) − v(x) = 15.41 nV
At an input of 0.675 V the output sits exactly at V_x: both halves see the same voltages, and the error is zero at the same point.
Input 900 mVv(out) − v(in) = -2.166 mV · v(out) − v(x) = 280 mV
At 0.9 V the gap is 0.280 V and the error −2.17 mV.
Input 1.2 Vv(out) − v(in) = -6.221 mV · v(out) − v(x) = 581.2 mV
Higher up the gap and the error both grow.

Read the plot as a table

Input	v(out) − v(in)	v(out) − v(x)
600 mV	982.8 µV	-131.9 mV
675.1 mV	-33.11 pV	15.41 nV
700 mV	-280.3 µV	38.96 mV
800 mV	-1.279 mV	172.4 mV
900 mV	-2.166 mV	280 mV
1 V	-3.114 mV	381.6 mV
1.1 V	-4.277 mV	481.9 mV
1.2 V	-6.221 mV	581.2 mV

Measured on ngspice 42 (the lab netlist, 651 points).

The zero sits at 0.675 V, below the tail's saturation edge of 0.811 V (E5.2), so you cannot simply run the OTA there. The cure is in the design: make the two drains sit at the same voltage by construction. E5.5 shows the sizing rule that does it in a two-stage op-amp.

Random offset: refer each mismatch to the input

Mismatch shifts each transistor's threshold and current factor by a small random amount, which shrinks as the device grows (E7.4 measures the law). This lesson replaces the randomness with one fixed number: a 1 mV source in series with one gate acts like a 1 mV threshold error in that device.

OTA-A as a buffer with two mismatch sourcesVM2 sits between the output and M2's gate, VM4 between node x and M4's gate.

The buffer
The output returns through VM2 to M2's gate, the − input. With both sources at 0 V this is the plain buffer: 2.17 mV low at 0.9 V.
A threshold error in the pair
VM2 = 1 mV lifts M2's gate 1 mV above the output, like a 1 mV lower threshold. The loop puts M2's gate back where balance needs it, so the output moves by −0.993 mV: one to one.
A threshold error in the load
VM4 = 1 mV weakens M4 by g_m4 × 1 mV of current. The pair must make that up with an input difference of g_m4/g_m2 × 1 mV, so the output moves by −0.565 mV.

Read the circuit as text

M3 PMOS transistor (8/1): gate → x, source → VDD, drain → x
VM4 voltage source (1 mV): + → n1, − → x
M4 PMOS transistor (8/1): gate → n1, source → VDD, drain → out
M1 NMOS transistor (10/1): gate → n2, drain → x, source → n3
M2 NMOS transistor (10/1): gate → n4, drain → out, source → n3
VM2 voltage source (1 mV): + → n4, − → out
IB current source (20 µA): + → VDD, − → n5
MB NMOS transistor (8/1): gate → n5, drain → n5, source → 0
M5 NMOS transistor (8/1): gate → n5, drain → n3, source → 0
C_L capacitor (1 pF): pin 1 → out, pin 2 → 0
out port: terminal → out
in port: terminal → n2

x = 0.618 V
out = 0.898 V

Operating point of the clean buffer at 0.9 V. NMOS bodies at ground, PMOS bodies at VDD. W/L in µm.

The lab runs one buffer per device, each with 1 mV in one gate, and compares it with the clean buffer.

1 mV at the gate of	Output shift	Predicted factor	Factor
M1 (pair, +)	+0.991 mV	1	1
M2 (pair, −)	−0.993 mV	1	1
M3 (mirror diode)	+0.557 mV	g_m3/g_m1	0.567
M4 (mirror output)	−0.565 mV	g_m4/g_m2	0.566

All from the lab netlist on ngspice 42; g_m values from the clean buffer's operating point.

A threshold error in the pair appears at the input one to one. An error in the load changes a current by g_m3ΔV_th; the pair must cancel that current, which takes an input of g_m3ΔV_th/g_m1. With g_m3/g_m1 = 0.567, the load counts more than half as much as the pair.

Independent random errors add as a root-sum-square. If each device had a threshold error with a standard deviation of 1 mV, the offset's standard deviation would be √(0.991² + 0.993² + 0.557² + 0.565²) mV = 1.61 mV. Making only the pair larger leaves the load's share untouched, which is why E7.5 finds that the load must grow too.

Asked in interviews

What is input offset voltage?
The differential input that puts the amplifier's output where the design wants it, modelled as a source in series with one input. A unity-gain buffer shows it directly as V_out − V_in; OTA-A gives −2.17 mV at 0.9 V.
Systematic against random offset?
Systematic offset comes from the schematic, such as unequal drain voltages in a mirror, and is the same on every chip: fix it in the design or trim it once. Random offset comes from mismatch, varies chip to chip, and shrinks as devices grow.
How does mismatch in the load refer to the input?
A threshold error ΔV_th in a mirror device changes its current by g_m,loadΔV_th. The pair cancels it with an input of (g_m,load/g_m,pair)·ΔV_th. Here that factor is 0.57, so the load matters almost as much as the pair.

Try it

Run the netlist. vos is the clean buffer's offset at 0.9 V and vos_hand the estimate −(V_out − V_x)/A₀. Each shift_m* is the output change for 1 mV at one gate, and k3, k4 are the g_m ratios that predict the load rows. vin_zero and gap_zero are the input levels where the offset and the drain gap cross zero.

Predict, then run. Set d4=2m on X4 and predict shift_m4 before you run. Set d3=1m d4=1m on X4: the two load errors nearly cancel (−8.5 µV), because they shift the whole mirror's gate together. Then make M3 and M4 longer inside .subckt otam and see whether the systematic offset shrinks.

SPICEngspice 42 · simulator service

Edit the netlist, then run it

Expected measurements: vos = -2.165886e-03 vos_hand = -2.042426e-03 shift_m1 = 9.910558e-04 shift_m2 = -9.927478e-04 shift_m3 = 5.567271e-04 shift_m4 = -5.652638e-04

Check yourself

Predict the outputAn ideal amplifier (an E source with gain 10⁹) has 2 mV of input offset, modelled by VOS in series with its + input. It sits in a non-inverting circuit with R_F = 9 kΩ and R_G = 1 kΩ, and its input is at 0 V. Type the line meas prints for v(out) (format: vout = 6.319360e-01).

* an ideal amplifier (gain 1e9) with 2 mV of input offset, in a gain-of-10 circuit
VIN in 0 0
VOS inp in 2m
E1 out 0 inp fb 1e9
RF out fb 9k
RG fb 0 1k
.control
dc VIN 0 0.1 0.05
meas dc vout FIND v(out) AT=0
.endc
.end

ConceptRead the drain-gap plot. At what input level is OTA-A's systematic offset zero, and can you simply bias it there?

At 1.274 V, the upper edge of the input range; no, M1 is in triode thereAt 0.9 V, mid-supply; yes, that is where it is usedAt 0.675 V, where v(out) = v(x); no, the tail is out of saturation thereNowhere: a five-transistor OTA always has offset

ConceptFour explanations are offered for OTA-A's −2.17 mV offset with identical devices. Which is right?

The buffer's finite gain leaves an error of 0.9 V divided by 136.6The tail carries 18.67 µA instead of the 20 µA that IB setsThe model gives M1 and M2 slightly different thresholds at randomM1/M2 and M3/M4 see different drain voltages, so their currents differ

ConceptWhich statement about removing offset is right?

Systematic offset is the same on every chip, so a design change removes it; random offset shrinks with device areaRandom offset is the same on every chip, so one trim value at test removes it for all partsNeither kind changes with device size; only a trim at test helpsSystematic offset shrinks with device area, because larger devices have smaller channel-length modulation

ConceptA 2 mV threshold error sits in M4, the mirror's output device. About how far does OTA-A's buffer output move?

Not at all: the diode M3 corrects itAbout 1.13 mV, twice the 1 mV resultAbout 2 mV, like an error in the pairAbout 0.27 V, the error times the gain

Remember

Input offset is the differential input that puts the output where the design wants it; a unity-gain buffer shows it as V_out − V_in, −2.17 mV for OTA-A.
Systematic offset is in the schematic: in a 5T OTA the output and the diode node sit at different voltages, and V_os ≈ −(V_out − V_x)/A₀.
A threshold error in the pair refers to the input one to one; in the load it refers by g_m,load/g_m,pair, 0.57 here, so the load matters almost as much.
Systematic offset is fixed by design; random offset varies from chip to chip and shrinks with device area (E7).