Capstone: a five-transistor OTA to spec

Turn an OTA brief into a sized netlist with the g_m/I_D method, check every line of the brief across the input range, and write the result as a datasheet with its margins.

Lesson: E5.7
Time: 40 min
Runs on: ngspice
Check: 5 questions

A bias loop needed an OTA with 40 dB of gain and 10 MHz of unity-gain frequency into 2 pF, from at most 20 µA. The first design sized its input pair by the square law and came out at 8.89 MHz. At the bottom of its input range, 0.7 V, it fell to 6.39 MHz.

AC analysisThe square-law first pass, open loopInput pair 5/1 from the square law, C_L = 2 pF, at two input levels.

at 0.9 V
at 0.7 V

Frequency 1 Hzat 0.9 V = 41.77 dB · at 0.7 V = 42.18 dB
The gain passes: 41.77 dB at 0.9 V and 42.18 dB at 0.7 V.
Frequency 6.391 MHzat 0.9 V = 2.871 dB · at 0.7 V = -0.005264 dB
At 0.7 V the gain reaches 0 dB at 6.39 MHz. The tail transistor has left saturation and carries less current, so g_m falls.
Frequency 8.894 MHzat 0.9 V = -0.001475 dB · at 0.7 V = -2.877 dB
At 0.9 V it reaches 0 dB at 8.89 MHz, short of the 10 MHz line.

Read the plot as a table

Frequency	at 0.9 V	at 0.7 V
1 Hz	41.77 dB	42.18 dB
10 Hz	41.77 dB	42.18 dB
100 Hz	41.77 dB	42.18 dB
1 kHz	41.77 dB	42.18 dB
10 kHz	41.69 dB	42.01 dB
100 kHz	37.15 dB	35.15 dB
1 MHz	18.96 dB	16.1 dB
6.391 MHz	2.871 dB	-0.005264 dB
8.894 MHz	-0.001475 dB	-2.877 dB
10 MHz	-1.02 dB	-3.896 dB
100 MHz	-21.38 dB	-24.4 dB
1 GHz	-48.67 dB	-53.77 dB

Every point is from a run on ngspice 42 (181 points). The same run holds the other sizings of the quiz.

A brief is met only when every line holds at every input level it names, with room to spare.

The brief and the design order

Line of the brief	Target
Supply	1.8 V, SKY130 tt, 27 °C
Load	C_L = 2 pF
DC gain A₀	≥ 40 dB
Unity-gain frequency f_u	≥ 10 MHz
Phase margin as a buffer	≥ 70°
Input range (every device saturated)	includes 0.7 V to 1.1 V, with gain and f_u met at both ends
Supply current, bias included	≤ 20 µA

Corners are the next step (E7.6). The input range follows E5.2: each edge is where a transistor leaves saturation.

The order matters, because each step fixes one number the next one needs. The figure walks it; the numbers are the ones this lesson's runs give.

Speed comes first. A five-transistor OTA driving a capacitor has one dominant pole at its output, so its gain falls 20 dB per decade and crosses 1 at f_u = g_m1/(2πC_L) (E5.3). The load is fixed by the brief, so f_u fixes g_m1. Nothing else in the design can buy that speed back.

Current comes second. The brief counts every microampere from the supply, the bias diode included. Keeping the bias branch small (2 µA) and copying it eight times into the tail leaves about 8 µA for each input device. Dividing the g_m you need by that current gives the g_m/I_D the pair must reach, which says how strongly inverted it may be.

Width, length and the input range follow. The chart turns g_m/I_D into a current density and so into a width. The gain line picks the channel length of M2 and M4, because it sets their g_ds. Last, the two edges of the input range from E5.2 check that the tail and the load leave every transistor in saturation from 0.7 V to 1.1 V.

From brief to sized OTAArrows show which number feeds the next decision.

Speed sets gm
Into a capacitive load, f_u = g_m1/(2πC_L), so g_m1 ≥ 2π × 10 MHz × 2 pF = 125.7 µS. The output node carries more than C_L, and the low end of the input range costs current, so aim 25 % higher: 157 µS.
Current sets gm/ID
Keep 2 µA for the bias diode and copy it eight times for a 16 µA tail: about 8 µA per input device. Then g_m/I_D ≥ 157/8 = 19.6 V⁻¹. Pick 22, in moderate inversion.
The chart sets W; gain sets L
The chart below gives 0.181 µA/µm at g_m/I_D = 22, so W = 8 µA / 0.181 µA/µm = 44 µm: take 40. Gain is g_m/(g_ds2 + g_ds4); at a fixed current only L moves the g_ds terms, and L = 1 µm clears 40 dB in E5.3's OTA.
Range, then simulate
The lower edge is V_GS1 + V_Dsat5: a wide pair keeps V_GS1 low and a wide tail (8 × 8/2) keeps V_Dsat5 low. The upper edge is VDD − V_SG3 + V_th1: a 4/1 load keeps V_SG3 small. Then run every line of the brief.

Read the diagram as text

fu and CL: 10 MHz into 2 pF
gm of M1 and M2: ≥ 125.7 µS; aim 157 µS
Current budget: 2 µA bias + 16 µA tail
gm/ID: ≥ 19.6 /V; pick 22
Width from chart: 0.181 µA/µm: W = 40 µm
Length for gain: L = 1 µm for M1-M4
Input range: tail 8 × 8/2, load 4/1
Simulate and compare: every line at 0.7, 0.9, 1.1 V

fu and CL → gm of M1 and M2: 2π·fu·CL
gm of M1 and M2 → gm/ID
Current budget → gm/ID: I_D ≈ 8 µA
gm/ID → Width from chart
Width from chart → Length for gain
Length for gain → Input range
Input range → Simulate and compare

Hand numbers come from formulas; the chart and the check come from runs.

Reading the chart instead of the square law

The square law gives g_m/I_D = 2/V_ov. With μC_ox = 198 µA/V² (E2.3), 125.7 µS from 8 µA needs V_ov = 0.127 V and W/L = 2I_D/(μC_oxV_ov²) = 5. That is the hook's 5/1 pair. It aimed exactly at the minimum, and it trusted a formula that does not know about weak inversion.

The g_m/I_D chart (E2.5) is measured instead. Below, a 40 µm device at L = 1 µm is fed a current density I_D/W. Its drain is held at 0.4 V, near the drain-source voltage M1 will see in the OTA.

DC sweepg_m/I_D against current density, NMOS L = 1 µmg_m from the model at each point, divided by the drain current. V_DS = 0.4 V, source and body at ground.

Current density ID/W, per µm 5 nAgm/ID = 25.49 /V
Deep in weak inversion the ratio tops out at 25.49 V⁻¹: current is exponential in V_GS there.
Current density ID/W, per µm 180.7 nAgm/ID = 22 /V
g_m/I_D = 22 at 0.181 µA/µm. At about 8 µA that is a width near 44 µm.
Current density ID/W, per µm 1.6 µAgm/ID = 15.11 /V
The 5/1 pair at 8 µA runs 1.6 µA/µm, where the chart reads 15.11 V⁻¹, a little below the square law's 2/V_ov = 15.7.

Read the plot as a table

Current density ID/W, per µm	gm/ID
5 nA	25.49 /V
10 nA	24.97 /V
100 nA	22.81 /V
180.7 nA	22 /V
1 µA	17.17 /V
1.6 µA	15.11 /V

Every point is from a run on ngspice 42 (1000 points).

In the finished OTA, M1 carries 7.689 µA and measures g_m/I_D = 22.36, against 22 from the chart. Its source sits on the tail node, above the body, which raises the ratio slightly; its drain voltage differs too. The chart gets within 2 %; the square law sized for the bare minimum, with nothing to absorb the extra capacitance at the output or the starved tail at 0.7 V.

The result as a datasheet

AC analysisThe reference OTA, open loop at 0.9 VIB 2 µA; MB 8/2 and M5 eight copies of it; M1 = M2 40/1; M3 = M4 4/1; C_L = 2 pF.

gain
phase

Frequency 1 Hzgain = 42.42 dB · phase = -0.0005642°
42.42 dB at low frequency: 2.4 dB above the line.
Frequency 10 MHzgain = 2.439 dB · phase = -92.68°
At 10 MHz the gain is still above 0 dB.
Frequency 13.25 MHzgain = -0.01425 dB · phase = -93.88°
Unity gain at 13.25 MHz. The phase is −93.9°, so a buffer has 86.1° of phase margin. The mirror pole sits far above.

Read the plot as a table

Frequency	gain	phase
1 Hz	42.42 dB	-0.0005642°
10 Hz	42.42 dB	-0.005713°
100 Hz	42.42 dB	-0.05714°
1 kHz	42.42 dB	-0.5714°
10 kHz	42.38 dB	-5.695°
100 kHz	39.43 dB	-44.94°
1 MHz	22.41 dB	-84.6°
10 MHz	2.439 dB	-92.68°
13.25 MHz	-0.01425 dB	-93.88°
100 MHz	-18.23 dB	-119.9°
1 GHz	-38.48 dB	-178.4°

Every point is from a run of the lab netlist on ngspice 42 (181 points).

Line	Target	Measured	Worst margin
Supply current	≤ 20 µA	17.32 µA	2.68 µA (13 %)
A₀ at 0.7 / 0.9 / 1.1 V	≥ 40 dB	42.51 / 42.42 / 41.94 dB	1.94 dB at 1.1 V
f_u at 0.7 / 0.9 / 1.1 V	≥ 10 MHz	12.47 / 13.25 / 13.23 MHz	2.47 MHz (25 %) at 0.7 V
Phase margin as a buffer	≥ 70°	86.1°	16.1°
Input range	0.7 V to 1.1 V	0.654 V to 1.195 V	46 mV at the bottom

The lab netlist, tt, 27 °C. Every line holds with margin; the input range's lower edge and A₀ at the top are the tightest.

Each margin was measured, not assumed, and each one names the knob that would buy more. The table also says where to look first when the brief tightens. A₀ is set by g_m/I_D and L, and moving L leaves f_u almost alone. f_u is set by g_m and C_L, which means current or g_m/I_D. The input range trades against both: a wider tail or pair buys headroom with capacitance.

Asked in interviews

Walk me through sizing an OTA for a given GBW and load.
g_m = 2π·GBW·C_L, plus margin for parasitics. Split the current budget, divide g_m by the current per device for g_m/I_D, read the current density from a chart at your L and get W. Pick L for the gain, check both input-range edges, simulate across the input range, and fix the one line that misses.
Where does g_m/I_D help over the square law?
At low current densities, in moderate and weak inversion, where 2/V_ov overpromises. The chart is measured, so it holds in every region; here it predicted 22 against 22.36 in the circuit.
Which specs trade against which?
At fixed current, longer devices raise gain and add capacitance. Higher g_m/I_D saves current but needs wider, slower devices; a wider input range needs lower V_Dsat and V_GS, which again means wider devices. Power buys f_u directly.

Try it

This is the worked answer. Four benches share one bias: open loop at 0.9 V (where the supply current is read), at 0.7 V and at 1.1 V, and a follower swept from 0.3 V to 1.5 V for the saturation edges. Every line of the datasheet table is one meas line.

Size it yourself: set w12=5 (the square-law pair) and watch fu and icmr_lo miss. Then try l34=2 and look at a0_11 and fu_11: a longer load raises V_SG3, and the top of the range collapses.

SPICEngspice 42 · simulator service

Edit the netlist, then run it

Expected measurements: i_supply = 1.731525e-05 gm1 = 1.719211e-04 gm_id = 2.235918e+01 id_1 = 7.689059e-06 a0_db = 4.242109e+01 fu = 1.325411e+07 pm = 8.613081e+01 a0_07 = 4.251073e+01 fu_07 = 1.246749e+07 a0_11 = 4.193624e+01 fu_11 = 1.322809e+07 icmr_lo = 6.543133e-01 icmr_hi = 1.194800e+00

Check yourself

Predict the outputAn ideal OTA, a G source of 251.3274 µS, drives only C_L = 2 pF. The run prints the gain magnitude at 10 MHz. Type the line meas prints (format: a = 6.319360e-01).

* an ideal OTA: g_m = 251.3274 uS into C_L = 2 pF, with 1 T ohm for a DC path
VIN in 0 DC 0 AC 1
G1 0 out in 0 251.3274u
CL out 0 2p
RL out 0 1T
.control
ac lin 3 5Meg 15Meg
let mag = mag(v(out))
meas ac a FIND mag AT=10Meg
.endc
.end

ConceptFour sizings on the reference bias (C_L = 2 pF, measured at 0.9 V unless stated). Which one meets the gain line but misses f_u at 0.9 V?

Pair 40/0.5, load 4/1Pair 40/1, load 4/1Pair 5/1, load 4/1Pair 40/1, load 4/2

ConceptAt a fixed tail current, which change raises the OTA's DC gain without moving f_u much?

Doubling the tail current, so every device carries twice as muchDoubling C_L, the load capacitance at the outputDoubling the width of the input pair M1 and M2, keeping their lengthDoubling L of all four pair and load devices, keeping each W/L

ConceptRead the final Bode plot: unity gain at 13.25 MHz with the phase at −93.9°. What phase margin does a buffer made of this OTA have?

86.1°, the distance from −180°93.9°, the phase itself3.9°, the distance from −90°76.1°, because the brief subtracts its 10° allowance

ConceptWhy did the square-law sizing come out short while the chart sizing met the brief?

The square law ignores the body effect, which halves g_m in a differential pairIts g_m target was the bare minimum, so output parasitics and the weaker tail at 0.7 V pushed f_u under the lineThe chart includes C_L, which the square law cannot knowThe square law gives too little g_m in weak inversion, so the pair ended up far too narrow

Remember

Design in order: f_u and C_L give g_m; the current budget gives g_m/I_D; the chart gives W; the gain gives L; the input range checks the tail and the load.
f_u = g_m/(2πC_L) needs margin: the output node carries more than C_L, and the tail current falls at the bottom of the input range.
A g_m/I_D chart is measured, so it sizes a device in any inversion region; here it predicted 22 against 22.36 in the circuit.
Check every line at every input level the brief names, and write the margins down: 17.32 µA, 41.94 dB, 12.47 MHz, 86.1° and 0.654 V to 1.195 V for the reference.