The five-transistor OTA

Load a differential pair with a current mirror, predict and measure its DC gain and unity-gain frequency, and tell the + input from the − input without guessing.

Lesson: E5.3
Time: 30 min
Runs on: ngspice
Check: 5 questions

A new designer wired an OTA as a buffer: the operating point put the output at 0.902 V, and AC analysis showed 42.7 dB of gain with +85° of phase at unity gain. The inputs were swapped, so the loop was positive feedback, and 0.902 V was a balance point that a real circuit leaves at once.

TransientTwo buffers from one OTA, one with its inputs swappedBoth start from the operating point. The input steps by 10 mV at 1 µs.

v(in)
right
swapped

Time 0 sv(in) = 900 mV · right = 897.8 mV · swapped = 902.2 mV
Both start where the DC solution put them: 0.898 V for the right buffer, 0.902 V for the swapped one.
Time 120 nsv(in) = 900 mV · right = 897.8 mV · swapped = 1.7 V
The swapped buffer passes 1.7 V after 0.12 µs, before the input has moved at all. The solver's rounding was enough to tip it.
Time 3 µsv(in) = 910 mV · right = 907.7 mV · swapped = 1.8 V
The right buffer has followed the 10 mV step to 0.908 V. The swapped one sits at the 1.8 V rail.

Read the plot as a table

Time	v(in)	right	swapped
0 s	900 mV	897.8 mV	902.2 mV
120 ns	900 mV	897.8 mV	1.7 V
500 ns	900 mV	897.8 mV	1.8 V
1 µs	900 mV	897.8 mV	1.8 V
1.5 µs	910 mV	907.7 mV	1.8 V
2 µs	910 mV	907.7 mV	1.8 V
2.5 µs	910 mV	907.7 mV	1.8 V
3 µs	910 mV	907.7 mV	1.8 V

Measured on ngspice 42 (1514 time points).

A DC solution says only that a balance exists; whether the circuit stays there depends on the sign of the feedback.

The mirror adds the two halves

Replace the two load resistors of E5.1 with a PMOS current mirror (E4.2 Ratios, PMOS mirrors and distributing bias). M3 is diode-connected on M1's side; M4 copies M3's current into M2's side, which is the single output.

OTA-A, the five-transistor OTAM1 to M5 plus the bias diode MB. The gate of M1 is the + input, the gate of M2 the − input.

Balance
Both inputs at 0.9 V. M1 and M2 each carry about 9.3 µA. M3 takes M1's current, M4 copies it, and M2 takes the copy away: no current is left for C_L.
I · I
Raise the + input
M1 pulls Δi more. M3 carries it, so M4 pushes Δi more into the output. M2 pulls Δi less, because the tail current is fixed. Both changes push the output up: 2Δi flows into C_L.
I + Δi · I + Δi · 2Δi
Raise the − input
Now M2 pulls more and M1 less, so M4 pushes less: the output falls. The gate on the diode side is +, the gate on the output side is −.

Read the circuit as text

M3 PMOS transistor (8/1): gate → x, source → VDD, drain → x
M4 PMOS transistor (8/1): gate → x, source → VDD, drain → out
M1 NMOS transistor (10/1): gate → n1, drain → x, source → tail
M2 NMOS transistor (10/1): gate → n2, drain → out, source → tail
IB current source (20 µA): + → VDD, − → n3
MB NMOS transistor (8/1): gate → n3, drain → n3, source → 0
M5 NMOS transistor (8/1): gate → n3, drain → tail, source → 0
C_L capacitor (1 pF): pin 1 → out, pin 2 → 0
out port: terminal → out
+ port: terminal → n1
− port: terminal → n2

x = 0.618 V
out = 0.898 V
tail = 0.204 V

Operating point of the lab at 0.9 V. NMOS bodies at ground, PMOS bodies at VDD. W/L in µm.

With resistor loads, each drain moves by g_mv_d/2 times its load. Here M1's half of the signal current is not lost in a resistor: the mirror copies it to the output, where it adds to M2's half. The whole g_mv_d reaches one node, so the differential-to-single-ended conversion costs nothing.

That output node sees M2's and M4's output resistances in parallel. So the DC gain is A₀ = g_m(r_o2 ∥ r_o4) = g_m2/(g_ds2 + g_ds4). An amplifier that turns a voltage into a current, with a gain set by the load it drives, is an operational transconductance amplifier (OTA).

Gain, bandwidth and the second pole

The lab runs OTA-A open loop. A 1 TH inductor from the output to the − input closes the loop at DC, so the output settles at its unity-gain level. A 1 F capacitor holds the − input still for AC; E6.5 explains when that trick misleads.

AC analysisOTA-A open loop into 1 pFGain and phase from the + input to the output.

gain
phase

Frequency 10 Hzgain = 42.71 dB · phase = -0.003049°
The DC gain A₀ is 42.71 dB, 136.6 V/V, with 0° of phase: the output follows the + input.
Frequency 187.5 kHzgain = 39.71 dB · phase = -44.97°
The output pole: the gain is 3 dB down at 187.5 kHz and the phase has reached −45°.
Frequency 25.53 MHzgain = -0.002124 dB · phase = -95.04°
The gain crosses 0 dB at f_u = 25.53 MHz, with a phase of −95.0°.

Read the plot as a table

Frequency	gain	phase
1 Hz	42.71 dB	-0.0002973°
10 Hz	42.71 dB	-0.003049°
100 Hz	42.71 dB	-0.0305°
1 kHz	42.71 dB	-0.305°
10 kHz	42.7 dB	-3.047°
100 kHz	41.63 dB	-28.03°
187.5 kHz	39.71 dB	-44.97°
1 MHz	28.04 dB	-79.57°
10 MHz	8.185 dB	-91.07°
25.53 MHz	-0.002124 dB	-95.04°
100 MHz	-12.57 dB	-109.5°
1 GHz	-38.63 dB	-145.5°

Measured on ngspice 42 (the lab netlist, 50 points per decade).

Quantity	Hand formula	Hand value	Measured
DC gain A₀	g_m2/(g_ds2 + g_ds4)	42.74 dB	42.71 dB
Unity-gain frequency f_u	g_m2/(2πC_L)	26.13 MHz	25.53 MHz
Gain-bandwidth A₀·f_-3dB	equals f_u for one pole	25.63 MHz	25.53 MHz

g_m2 = 164.2 µS, g_ds2 = 0.901 µS, g_ds4 = 0.296 µS from the lab's operating point.

Gain needs g_m and output resistance; bandwidth needs g_m and a small C_L. The output pole sits at 1/(2π(r_o2 ∥ r_o4)C_L), so f_u = A₀·f_-3dB = g_m/(2πC_L) does not depend on r_o at all.

Hand and run agree within 2.3 %: the formula keeps only g_m and C_L, while the run includes every device capacitance. The mirror also adds a second pole at node x, about g_m3/(2πC_x). The phase at f_u is −95.0°, only 5° past a single pole, so that pole sits far above f_u. A buffer made from this OTA is very stable; E6 names that 85° the phase margin.

To raise the gain without more current, raise r_o: make the devices longer. Doubling W and L of M1 to M4 lifts A₀ from 42.71 to 44.16 dB, only 1.18×. M4's g_ds falls from 0.296 to 0.131 µS, but M2's barely moves (0.901 to 0.920 µS). The larger devices also load node x: the phase at f_u drops to −107.9°.

Which input is which

Rule: in an OTA with an NMOS pair and a PMOS mirror load, the gate on the diode side (M1) is +, and the gate on the output side (M2) is −. Do not trust a netlist's node names; check the sign.

DC: open loop
With the loop open, raise the + input by 1 mV: the output must rise, by about A₀ millivolts.
AC: low-frequency phase
From + to the output the phase at low frequency is 0°; from − it is 180°. The lab prints ph10, the phase at 10 Hz: −0.003°.

A closed-loop DC check cannot tell. A buffer with swapped inputs still has a balance point near its input, because the balance equation does not care about the sign of the feedback. The hook's 0.902 V was exactly that.

Input on +, output fed back to −

VIP inp 0 DC 0.9 AC 1
XM1 x inp tail 0 sky130_fd_pr__nfet_01v8 W=10 L=1
XM2 out inn tail 0 sky130_fd_pr__nfet_01v8 W=10 L=1
LF out inn 1T

Output 0.898 V; phase 0° at 10 Hz and −95.0° at f_u. Negative feedback.

Input on −, output fed back to +

VIN inn 0 DC 0.9 AC 1
XM1 x inp tail 0 sky130_fd_pr__nfet_01v8 W=10 L=1
XM2 out inn tail 0 sky130_fd_pr__nfet_01v8 W=10 L=1
LF out inp 1T

Output 1.800 V, or 0.902 V with .nodeset v(out)=0.9; then 42.73 dB, phase 180° at 10 Hz and +85.2° at f_u. Positive feedback.

Both on ngspice 42. The swapped bench still converges: a DC run cannot catch the sign.

Asked in interviews

Draw a five-transistor OTA and mark the inputs.
An NMOS pair on a tail current source, with a PMOS mirror as the load. The diode-connected PMOS sits on M1's side, the output on M2's side. M1's gate is +, M2's gate is −: raising + pulls more current through the diode, which the mirror copies to the output.
What are its DC gain and unity-gain frequency?
A₀ = g_m1(r_o2 ∥ r_o4); f_u = g_m1/(2πC_L). Gain depends on output resistance, gain-bandwidth only on g_m and the load. OTA-A gives 42.71 dB and 25.53 MHz into 1 pF.
Where is the second pole, and how do you raise the gain without more power?
At the mirror's diode node, about g_m3/(2πC_x), where C_x is the gate capacitance of M3 and M4 plus M1's drain. Raise the gain with longer devices or cascodes, which raise r_o; longer devices lower that pole, so the phase at f_u gets worse.

Try it

Run the netlist. a0, f3db, fu and ph_fu read the Bode plot; gbw is A₀·f_-3dB; a0_hand and fu_hand are the formulas from M2's and M4's operating point. isup is the supply current, 38.67 µA, printed as −i(VDD) because SPICE counts current into the + terminal of VDD as positive.

Predict, then run. Set CL out 0 2p: A₀ stays and f_u should halve. Make M1 to M4 twice as wide and twice as long: A₀ rises a little and the phase at f_u falls. Then swap inp and inn on the VIP, LF and CF lines and read vout and ph10: the output sits at the 1.8 V rail and some measurements fail. Add .nodeset v(out)=0.9 and it balances at 0.902 V, with ph10 near 180°.

SPICEngspice 42 · simulator service

Edit the netlist, then run it

Expected measurements: a0 = 4.271332e+01 f3db = 1.875369e+05 fu = 2.553041e+07 ph_fu = -9.503574e+01 ph10 = -3.049303e-03 gbw = 2.563024e+07 a0_hand = 4.274152e+01 fu_hand = 2.613078e+07

Check yourself

Predict the outputThe same OTA-A, but the AC input drives M2's gate and the loop closes at DC to M1's gate. The run prints the real part of v(out) at 10 Hz divided by its magnitude: the sign of the low-frequency gain. Type the line meas prints (format: sgn10 = 6.319360e-01).

* OTA-A open loop: the AC input on M2's gate
.lib sky130 tt
VDD vdd 0 1.8
IB vdd nb 20u
XMB nb nb 0 0 sky130_fd_pr__nfet_01v8 W=8 L=1
XM5 tail nb 0 0 sky130_fd_pr__nfet_01v8 W=8 L=1
XM1 x inp tail 0 sky130_fd_pr__nfet_01v8 W=10 L=1
XM2 out inn tail 0 sky130_fd_pr__nfet_01v8 W=10 L=1
XM3 x x vdd vdd sky130_fd_pr__pfet_01v8 W=8 L=1
XM4 out x vdd vdd sky130_fd_pr__pfet_01v8 W=8 L=1
CL out 0 1p
VIN inn 0 DC 0.9 AC 1
LF out inp 1T
CF inp 0 1
.nodeset v(out)=0.9
.control
ac dec 10 10 100
let s=real(v(out))/mag(v(out))
meas ac sgn10 FIND s AT=10
.endc
.end

ConceptRead the Bode plot: A₀ = 42.71 dB (136.6 V/V) and f_-3dB = 187.5 kHz. What is their product, and what does it predict?

About 1.4 MHz, the second pole at node xAbout 8.0 MHz (42.71 × 187.5 kHz), the phase-margin frequencyAbout 25.6 MHz, the unity-gain frequency f_uAbout 25.6 GHz, the transistors' f_T

ConceptWhat sets the unity-gain frequency of OTA-A, to first order?

The output resistance r_o2 ∥ r_o4 and the load C_LThe DC gain A₀, and nothing elseThe second pole, at the mirror's diode node xThe input pair's g_m and the load capacitance C_L

ConceptOTA-A (M1's gate is +, M2's gate is −) is wired as a unity-gain buffer. Which connection gives positive feedback?

Input on M2's gate, output wired to M1's gateInput on M1's gate, output wired to M2's gateInput on M1's gate, output wired to M2's gate through 1 THInput on M1's gate through 10 kΩ, output wired to M2's gate

ConceptWhy does the mirror load give the whole g_mv_d at one output, where a single resistor-loaded drain gives half?

M4 amplifies M2's current by its own g_mM1's change is copied by the mirror to the output, where it adds to M2's changeThe PMOS mirror has twice the output resistance of the resistor that it replacesThe mirror doubles the tail current, so g_m doubles

Remember

A current-mirror load copies M1's current change to the output, so the full g_mv_d reaches one node: A₀ = g_m(r_o2 ∥ r_o4), 42.71 dB for OTA-A.
The output pole sets f_-3dB; the unity-gain frequency f_u = g_m/(2πC_L) does not depend on r_o: 25.53 MHz measured, 26.13 MHz by hand.
The mirror's diode node adds a second pole far above f_u, so the phase at f_u is only −95°.
The gate on the diode side is +, the gate on the output side is −; check the sign open loop or by the low-frequency phase, because a buffer with swapped inputs still converges.