Slew rate and output swing
Drive a two-stage op-amp with a large step, measure how fast each edge can move and what limits it, and find the output range the second stage really covers.
- Lesson
- E5.6
- Time
- 30 min
- Runs on
- ngspice
- Check
- 5 questions
A buffer passed every small-signal test, with 21 MHz of unity-gain bandwidth and a well-behaved 10 mV step, and then turned a 0.4 V peak-to-peak, 15 MHz sine into a lopsided triangle. Small-signal analysis treats the circuit as linear. A large, fast input pushes the input pair past its linear range, and then the output can only move as fast as a fixed current charges a capacitor.
- v(in)
- v(out)
- Time 400 nsv(in) = 1.03 V · v(out) = 814.1 mV
The input is a sine. Its steepest point needs 18.85 V/µs.
- Time 500 nsv(in) = 1.03 V · v(out) = 1.163 V
The output moves in straight lines: up at 17.84 V/µs and down at only 11.05 V/µs where it crosses 1 V. It cannot keep up, so its peak-to-peak shrinks to 0.371 V.
Read the plot as a table
| Time | v(in) | v(out) |
|---|---|---|
| 0 s | 1.03 V | 1.03 V |
| 100 ns | 1.03 V | 1.161 V |
| 200 ns | 1.03 V | 814 mV |
| 300 ns | 1.03 V | 1.163 V |
| 400 ns | 1.03 V | 814.1 mV |
| 500 ns | 1.03 V | 1.163 V |
| 600 ns | 1.03 V | 814 mV |
Every point is from a run on ngspice 42 (2408 time points). The 2 MHz copy in the same run follows its input.
Each edge of a large signal has a speed limit, the slew rate, and the two edges of this op-amp have different ones.
A small step and a large step
Put a 10 mV step and a 400 mV step into two copies of the buffer, and show each output in percent of its own step. A linear circuit gives two identical curves, because doubling the input doubles every point of the output.
- input
- 10 mV step
- 400 mV step
- Time 62.7 nsinput = 100% · 10 mV step = 89.96% · 400 mV step = 45.47%
The 10 mV step reaches 90 % after 9.08 ns from its 10 % point. It overshoots to 107.7 % and settles: a small-signal answer, set by fu and the phase margin (E6.3).
- Time 75.2 nsinput = 100% · 10 mV step = 106.4% · 400 mV step = 89.92%
The 400 mV step needs 20.78 ns for the same 10-90 %. Its output is a straight ramp: the circuit is no longer linear.
Read the plot as a table
| Time | input | 10 mV step | 400 mV step |
|---|---|---|---|
| 0 s | 0% | -1.425% | -0.0354% |
| 50 ns | 0% | -1.425% | -0.0354% |
| 62.7 ns | 100% | 89.96% | 45.47% |
| 75.2 ns | 100% | 106.4% | 89.92% |
| 100 ns | 100% | 98.35% | 100.1% |
| 150 ns | 100% | 98.55% | 99.63% |
| 200 ns | 100% | 98.55% | 99.62% |
| 250 ns | 100% | 98.55% | 99.62% |
| 300 ns | 100% | 98.55% | 99.62% |
Every point is from a run on ngspice 42 (1214 time points).
Here is why. A step of 400 mV appears almost entirely between the two gates at first, because the output has not moved yet. The pair of E5.1 steers all of the tail current ISS to one side once the difference passes a few hundred millivolts. It can never deliver more than ISS. That current charges Cc, so the output ramps at a fixed rate: SR = ISS/Cc.
A 10 mV step stays inside the pair's linear range. The current that flows is proportional to the error, so the response stays the scaled small-signal one, however fast it is.
Where the current goes on each edge
- Rising edge: M2 takes it all
The input jumps above the output, so M2 carries all of M5's current and M1 turns off; with M1 off, M3 and M4 carry nothing. M2 pulls the tail current, 19.57 µA, out of o1, and Cc supplies nearly all of it: the output side of Cc must rise.
ISS into Cc · ISS
- Rising edge: M6 has current to spare
M6 is a PMOS that turns on harder as o1 falls, so it can supply the output whatever CL asks. Cc sets the pace: SR = ISS/Cc.
M6 charges CL
- Falling edge: M1 takes it all
The input drops below the output. M1 carries the tail current, M3 and M4 copy it, and M4 pushes it into o1. o1 rises and M6 turns almost off.
ISS into o1
- Falling edge: M7 is the limit
Only M7 pulls the output down, with its fixed 41.13 µA. It must discharge CL and also take the current Cc pushes into the output as o1 climbs.
I7 = 41.13 µA · Cc current
Read the circuit as text
- IB current source (20 µA): + →
VDD, − →n1 - MB NMOS transistor (8/1): gate →
n1, drain →n1, source →0 - M3 PMOS transistor (8/1): gate →
n2, source →VDD, drain →n2 - M4 PMOS transistor (8/1): gate →
n2, source →VDD, drain →n3 - M1 NMOS transistor (10/1): gate →
n4, drain →n2, source →n5 - M2 NMOS transistor (10/1): gate →
n6, drain →n3, source →n5 - M5 NMOS transistor (8/1): gate →
n1, drain →n5, source →0 - M6 PMOS transistor (32/1): gate →
n3, source →VDD, drain →n7 - M7 NMOS transistor (16/1): gate →
n1, drain →n7, source →0 - R_z resistor (5 kΩ): pin 1 →
n3, pin 2 →n8 - C_c capacitor (1 pF): pin 1 →
n8, pin 2 →n7 - C_L capacitor (2 pF): pin 1 →
n7, pin 2 →0 - − inn port: terminal →
n4 - + inp port: terminal →
n6 - out port: terminal →
n7
Same parts and values as E5.5 (W/L in µm). The currents are the lab's values at the middle of each edge.
The lab measures the slope at the middle of each edge (vout = 1.05 V) and the currents at that instant.
| Edge | Hand formula | Hand value | Measured slope | 10-90 % of 0.4 V |
|---|---|---|---|---|
| Rising | ISS/Cc | 19.57 µA / 1 pF = 19.6 V/µs | 18.01 V/µs | 20.79 ns |
| Falling, if o1 stood still | I7/(CL + Cc) | 41.13 µA / 3 pF = 13.7 V/µs | 11.13 V/µs | 28.55 ns |
| Falling, if Cc took all of ISS | (I7 − ISS)/CL | (41.13 − 19.07) µA / 2 pF = 11.0 V/µs | 11.13 V/µs | 28.55 ns |
The lab netlist. ISS is M5's current at the middle of each edge (19.57 µA rising, 19.07 µA falling); I7 is M7's during the fall.
The falling edge is slower than even the first falling formula, which treats Cc as a second load because it assumes o1 stands still. But M4 drives o1 upward at 5.73 V/µs while the output falls at 11.13 V/µs. The voltage across Cc changes by both, so it carries 1 pF × 16.86 V/µs = 16.86 µA into the output. CL needs 2 pF × 11.13 V/µs = 22.25 µA. Together that is 39.11 µA of M7's 41.13 µA; M6 still supplies 0.77 µA and the rest charges the transistors' own capacitance.
Most of M4's ISS flows on through Cc, so the better hand rule leaves M7 only I7 − ISS for CL: 11.0 V/µs, within 1 % of the run.
Output swing and full-power bandwidth
The output swing is the range the output covers while the op-amp is still an amplifier. The hand rule: M7 needs VDS above its saturation voltage, and M6 needs VSD above its own. That gives VDsat7 to VDD − VSDsat6, 0.134 V to 1.614 V here.
A buffer cannot show it, because its input moves with its output. The figure sweeps a buffer and an inverting amplifier of gain −1 (100 kΩ in, 100 kΩ feedback, + input at 0.9 V), whose inputs stay near 0.9 V.
- buffer
- inverting
- Input 1.33 Vbuffer = 1.32 V · inverting = 469.9 mV
The buffer leaves its input by 10 mV at 1.330 V. This is the top of the input range: M2's drain, o1, is too low for its gate (E5.2).
- Input 1.4 Vbuffer = 1.37 V · inverting = 400.1 mV
At 1.4 V in, the buffer gives 1.370 V. The inverter, with its inputs parked at 0.9 V, still tracks: its output is 0.400 V.
- Input 1.8 Vbuffer = 1.476 V · inverting = 19.24 mV
The inverter stays within 10 mV of 1.8 V − vin from 0.019 V to 1.747 V of output.
Read the plot as a table
| Input | buffer | inverting |
|---|---|---|
| 0 V | 15.61 nV | 1.756 V |
| 200 mV | 195.3 mV | 1.599 V |
| 400 mV | 397.1 mV | 1.399 V |
| 600 mV | 599 mV | 1.2 V |
| 800 mV | 799.8 mV | 999.7 mV |
| 1 V | 999.9 mV | 799.8 mV |
| 1.2 V | 1.199 V | 599.9 mV |
| 1.33 V | 1.32 V | 469.9 mV |
| 1.4 V | 1.37 V | 400.1 mV |
| 1.6 V | 1.447 V | 200.3 mV |
| 1.8 V | 1.476 V | 19.24 mV |
Every point is from a run on ngspice 42 (181 points). The open-loop sweep in the same netlist gives the gain edges.
So the brief's 1.4 V buffer stops at 1.370 V because of the input range, not the output stage. But tracking within 10 mV flatters the output too: a loop with 80 dB to spare hides a gain that has fallen a long way. Sweep the op-amp open loop instead. Its gain peaks at 11 022 and falls to half at 0.293 V and 1.489 V of output. That is well inside the hand rule's 0.134 V to 1.614 V. ro drops long before a device leaves saturation (E2.4).
Slew rate also limits large sines. A sine of amplitude A at frequency f has a steepest slope of 2πfA. The full-power bandwidth is the frequency where that equals the slew rate: f = SR/(2πA). For A = 0.2 V and the falling 11.13 V/µs it is 8.85 MHz.
| Sine, 0.2 V amplitude | Slope needed | Output rises at | Output falls at | Output peak-to-peak |
|---|---|---|---|---|
| 2 MHz | 2.51 V/µs | 2.50 V/µs | 2.52 V/µs | 0.399 V |
| 15 MHz | 18.85 V/µs | 17.84 V/µs | 11.05 V/µs | 0.371 V |
The hook's run: slopes where each output crosses its middle.
Asked in interviews
What is slew rate and what sets it in a two-stage op-amp?
The largest rate at which the output can change, in V/µs. A large input steers the whole tail current to one side, which charges Cc: SR = ISS/Cc. The falling edge can be limited by the second stage's fixed sink: about (I7 − ISS)/CL, because M7 also takes Cc's current. Here 18.0 V/µs up and 11.1 V/µs down.
Slew rate or bandwidth: which one limits a waveform?
Change the amplitude. A bandwidth limit scales: half the input, half the output, same shape. A slew limit does not: small signals pass clean while large ones turn into ramps and triangles. A sine slews above f = SR/(2πA).
What is the output swing of a class-A output stage?
About VDsat of the sink above ground to VDD − VSDsat of the source device, by the hand rule. Measured by where the open-loop gain halves it is narrower: 0.293 V to 1.489 V here, against 0.134 V to 1.614 V.
Try it
Run it and open Plots: v(out) ramps up, ramps down more slowly and dips before it settles. sr_rise and sr_fall are the slopes in V/µs where the output crosses 1.05 V; i5_rise, i6_fall and i7_fall are the currents at those instants.
Now set cc=2p and predict sr_rise before you run: the tail current is the same, so the rising slope should halve. Then put cc back and set w7=32. M7 sinks twice the current: watch the falling slope and the dip.
Run the netlist to draw its plots here.
t_rise = 2.079081e-08 targ= 1.252464e-07 trig= 1.044556e-07 t_fall = 2.854566e-08 targ= 8.362279e-07 trig= 8.076822e-07 sr_rise = 1.800529e+01 i5_rise = 1.956792e-05 sr_fall = -1.112602e+01 so1_fall = 5.729085e+00 i6_fall = 7.668806e-07 i7_fall = 4.113176e-05 o1_max = 8.975112e-01 at= 8.301000e-07 v_min = 7.330763e-01 at= 8.481000e-07 v_end = 8.498584e-01 i5_fall = 1.906927e-05 i5_min = 1.751144e-05 at= 8.471000e-07Check yourself
Remember
- A large input steers the whole tail current to one side; the first stage then charges Cc at SR = ISS/Cc, 18.0 V/µs measured in OPA-B.
- The falling edge is limited by M7, which must discharge CL and take Cc's current as o1 rises: 11.1 V/µs, close to (I7 − ISS)/CL = 11.0 V/µs and below the 13.7 V/µs of I7/(CL + Cc).
- A small signal never slews; a sine of amplitude A slews above the full-power bandwidth f = SR/(2πA).
- Output swing is where the open-loop gain falls, 0.29 V to 1.49 V here; a closed-loop test and the VDsat rule both flatter it, and a buffer is limited first by its input range.