The two-stage op-amp

Two stages, two jobs

One stage with a cascode could raise the gain, but on a 1.8 V supply the stacked devices leave little room for the output to swing. The two-stage op-amp splits the jobs between two simpler stages. Stage one is the OTA of E5.3: it takes the differential input and gives gain. Stage two is a common-source stage: more gain, and an output that can swing close to both rails (E5.6).

Each stage is a transconductance driving a resistance: stage one is g_m2 into r_o2 ∥ r_o4, and stage two is g_m6 into r_o6 ∥ r_o7. With g = 1/r_o (the output conductance g_ds), the DC gain is the product A₀ = A₁·A₂. The lab reads every g_m and g_ds from the operating point.

A Bode plot draws gain in dB and phase against frequency on a log axis, and the open-loop one shows both numbers at work. Step through it and read each stop.

C_c is what keeps that phase above −180° near f_u. Shrink it to 1 aF and the gain crosses 0 dB at 66.27 MHz with the phase at −194.9°: a buffer made of that op-amp would oscillate. E6.4 explains why.

Where stage one's output must sit

Stage two decides the voltage at o1. M7 sinks a fixed current, so o1 must settle at the V_SG that makes M6 carry exactly that current. Stage one works without error only when o1 sits where node x sits. Then M1 and M2, and M3 and M4, see the same drain voltages and carry the same currents.

M6 sits on the same supply as M4 and is driven from M4's drain. Give M6 the same current per unit W/L as M4 and its V_SG equals M4's, which equals M3's, so V_o1 = V_x. M4 carries half of M5's current and M7 copies M5 by width, so the sizing rule is (W/L)₆/(W/L)₄ = 2(W/L)₇/(W/L)₅. OPA-B keeps it: 32/8 = 2 × 16/8.

Any gap between o1 and x shows up at the input divided by stage one's gain: V_os ≈ (V_o1 − V_x)/A₁. The input offset V_os is v_out − v_in of the buffer. The lab measures V_o1 = 0.6030 V and V_x = 0.6182 V, so −15.2 mV/114.1 = −0.133 mV, against −0.132 mV measured.

The rule is a first-order estimate, and the simulator says how far it is off. The zero sits between 32/1 and 48/1 because M7 carries 40.87 µA, 2.19 times M5's 18.67 µA, not 2 times. M7 sits at 0.9 V and M5 at 0.204 V, and channel-length modulation (E2.4) gives the device with more V_DS more current. The PMOS side adds to it: M4 has 1.20 V across it and M6 only 0.90 V, so M6 carries less current per W/L than M4 at the same V_SG. Both effects call for a wider M6.

XM6 out o1 vdd vdd sky130_fd_pr__pfet_01v8 W=24 L=1
XM7 out nb 0 0 sky130_fd_pr__nfet_01v8 W=16 L=1

XM6 out o1 vdd vdd sky130_fd_pr__pfet_01v8 W=32 L=1
XM7 out nb 0 0 sky130_fd_pr__nfet_01v8 W=16 L=1

Two stages cost current: OPA-B draws 79.54 µA from 1.8 V, or 143 µW, made of 20 µA of bias, 18.67 µA in stage one and 40.87 µA in stage two.

Try it

Run it. op prints nothing; it stores each g_m and g_ds, and meas reads them back through the AC plot as stage gains. offset is v_out − v_inp at DC, where the inductor ties out to the − input: the buffer's offset. The last two lines repeat the AC run with C_c shrunk to 1 aF.

Now break the rule: set w6=24 and predict the sign of offset before you run. Then set L = 2 for M6 and M7 (keep W/L by doubling W) and watch stage2 rise. E5.6 shows what the longer devices cost in output swing.

Check yourself

* OPA-B open loop: M2's gate at 0.9 V, M1's gate at the balance level plus VSTEP
.lib sky130 tt
VDD vdd 0 1.8
IB vdd nb 20u
XMB nb nb 0 0 sky130_fd_pr__nfet_01v8 W=8 L=1
XM5 tail nb 0 0 sky130_fd_pr__nfet_01v8 W=8 L=1
XM1 x g1 tail 0 sky130_fd_pr__nfet_01v8 W=10 L=1
XM2 o1 g2 tail 0 sky130_fd_pr__nfet_01v8 W=10 L=1
XM3 x x vdd vdd sky130_fd_pr__pfet_01v8 W=8 L=1
XM4 o1 x vdd vdd sky130_fd_pr__pfet_01v8 W=8 L=1
XM6 out o1 vdd vdd sky130_fd_pr__pfet_01v8 W=32 L=1
XM7 out nb 0 0 sky130_fd_pr__nfet_01v8 W=16 L=1
RZ o1 z 5k
CC z out 1p
CL out 0 2p
VG2 g2 0 0.9
VBAL gb 0 0.8998682
VSTEP g1 gb 0
.control
dc VSTEP 0 1m 1m
* the output in volts, rounded to a whole volt
let vr = floor(v(out)+0.5)
meas dc vout FIND vr AT=1m
.endc
.end