ASIC Point
Yosys · OpenROAD · KLayout

RTL → GDSII

Take a small single-clock RTL design through synthesis, placement and routing to a downloadable SKY130 GDSII layout. Free, no sign-up.

  1. 1SynthesisWaiting
  2. 2FloorplanWaiting
  3. 3Global placementWaiting
  4. 4LegalizationWaiting
  5. 5Clock treeWaiting
  6. 6Global routeWaiting
  7. 7Detailed routeWaiting
  8. 8GDSIIWaiting
Synthesizable RTLmain.sv

Ready. Ctrl/⌘+Enter runs the flow.

Design limits and timing assumptions

Use synthesizable Verilog or the Yosys native SystemVerilog subset. One scalar input must clock every flip-flop directly. Use reset for startup values. Flop initializers, latches, gated clocks, bidirectional ports, testbenches and delay statements are outside this flow.

Up to 600 mapped cells and 128 signal pins. The clock period can be 1–100 ns. Input and output maximum delays are one tenth of that period; minimum delays are 0 ns. Clock transition is 0.1 ns and output load is 0.01 pF.

The square core targets 40% utilization, with at least 50 µm per side for the power grid. Timing uses the TT 1.80 V, 25 °C library and extracted routing parasitics. DRC and LVS sign-off are not run.

Detailed routing has a 240-second limit. A busy service may queue your design first. Keep this tab open. Files are removed from the server after the job; this editor stays in memory until you leave the page.

Routed layout

Multiply. Accumulate. Make silicon.

Run the 4-bit MAC to see its pipeline become placed cells and routed metal.

The viewer shows cell placement and interconnect from the routed DEF. The GDSII download also contains the cell geometry. DRC/LVS sign-off is outside this playground.