AXI4-Lite, AXI3 and AXI5: the family

Know what AXI4-Lite keeps and drops, drive a register block on Lite, say what a burst does to a Lite subordinate and what a converter must do about it, and place AXI3, AXI4 and AXI5 side by side.

Lesson: P2.15
Time: 30 min
Runs on: Your browser
Check: 6 questions

A DMA engine wrote a four-beat burst to a register block on AXI4-Lite: the block took the address and the first data beat, answered OKAY, and went back to idle. The engine then waited for beat 1 to be taken, which never happened, because a Lite subordinate has no idea of a burst and the transaction was over for it. Nothing in the block was wrong. The system had put a full AXI manager in front of a Lite subordinate with no converter in between, and the first burst found the gap.

What AXI4-Lite keeps and drops

AXI4-Lite is the register-interface subset of AXI4, so that a control block with a dozen registers need not implement bursts, lane steering and reordering. The specification defines it in four sentences. Every transaction has burst length 1. Every access uses the full width of the bus, 32 or 64 bits. Every access is Non-modifiable and Non-bufferable, and exclusive accesses are not supported.

Channel	Kept	Dropped, and what the value is taken to be
Global	ACLK, ARESETn
Write address	AWADDR, AWPROT, AWVALID, AWREADY	AWID (no IDs), AWLEN (0), AWSIZE (the bus width), AWBURST (meaningless), AWLOCK (0), AWCACHE (0b0000), AWQOS, AWREGION, AWUSER
Write data	WDATA, WSTRB, WVALID, WREADY	WLAST (1)
Write response	BRESP, BVALID, BREADY	BID; the EXOKAY response is never used
Read address	ARADDR, ARPROT, ARVALID, ARREADY	ARID, ARLEN (0), ARSIZE, ARBURST, ARLOCK, ARCACHE, ARQOS, ARREGION, ARUSER
Read data	RDATA, RRESP, RVALID, RREADY	RID, RLAST (1); EXOKAY never used

The AXI4-Lite signal set. The handshakes, the strobes, the protection bits and the responses survive; the burst machinery and the IDs do not.

Three details are easy to get wrong. Write strobes are kept. A subordinate may use them, ignore them and treat every write as full width, or reject combinations it does not support; a subordinate that is memory must honour them. Multiple outstanding transactions are allowed, limited by the READY signals. And there are no IDs, so responses come back in request order. A Lite subordinate that sits on a full AXI interface must reflect the ID it was given, AWID on BID and ARID on RID. The manager matches responses by ID.

A register block on Lite

The bench of this lesson replaces the memory with axi_lite_regs, four 32-bit registers. CTRL and DATA at 0x0 and 0x4 are read/write, STATUS at 0x8 and ID at 0xc are read-only, and an offset at 0x10 or above is outside the block. The block is the Lite subset exactly. It waits for the address and the data of a write, performs it and answers once. It answers a read in the next cycle. It reflects IDs so the full-AXI task library can drive it, and it holds RLAST at 1, which is what a Lite transfer means.

Run the example and read the printed lines and the dump. A write to STATUS is answered SLVERR, a contained error from the subordinate that owns the address, and nothing changes. A read of ID returns 0x4c495445, which spells LITE read from the lowest address up, as the dump shows: 45 54 49 4c. Without ID reflection the task library's b_wait(id) would match nothing, and a manager with several IDs in flight would attribute the response to the wrong transaction.

A burst meets a Lite subordinate

Now the opening story, on the bench. A four-beat read goes straight into the register block:

Four beats asked of a block that knows only single transfers.

axi_read(0, 32'h0, 3, 2, INCR);     // a 4-beat burst into a Lite subordinate
$display("beats received: %0d", last_beats);

Measured: one transfer with RLAST, and the checker names the rule.

e3 AR id=0 addr=0x0 len=3 size=2 INCR
RULE rlast broken at edge 4: RLAST on beat 0 of the oldest read with id 0, whose ARLEN is 3
e4 R  id=0 beat 0 data=0x0 OKAY last  addr 0x0 lanes 0-3
beats received: 1
checker: 0 writes, 1 reads, 0 stalled edges, 1 rules broken

Who is at fault? Neither side, by its own rules: the block is a correct Lite subordinate and the manager issued a legal AXI4 read. The system is wrong, and the specification offers three remedies. Conversion: a bridge turns every AXI transaction into Lite-shaped ones. Protection: a bridge refuses anything outside the subset with a compliant error response, which for a read burst means an error on every beat and RLAST in place. Detection: let the access through and tell software. Conversion costs the most gates and survives uses nobody foresaw.

A converting bridge follows fixed rules. A burst becomes one transaction per beat, each at the address the burst type gives that beat. The responses of the generated writes are combined into one B, and any error is sticky. One SLVERR among four OKAYs gives SLVERR, and with both SLVERR and DECERR the first received wins. A wide transaction is split at Lite-width boundaries; a narrower one passes as it is. Strobes pass unchanged. AxLOCK is discarded, so an exclusive write through a bridge must fail. AxCACHE is discarded, which is legal: Modifiable may be treated as Non-modifiable and Bufferable as Non-bufferable. AxPROT passes. WLAST is dropped and RLAST is implied on every read transfer.

A four-beat write through a converting bridgeArrows carry requests from the manager through the bridge to the register block; return moves are responses.

The burst arrives
The manager issues one write of four beats at 0x00. The bridge accepts it as a full AXI subordinate would; a burst for the DRAM would pass through untouched.
Follow the calls, values and waits
1. data AW 0x00, 4 beats: AXI manager → Lite bridge
Four single transfers
The bridge issues four Lite writes, one per beat, at 0x00, 0x04, 0x08 and 0x0c: the addresses of the INCR burst.
More context
Strobes and AxPROT pass; WLAST, AxLOCK and AxCACHE are dropped.
Follow the calls, values and waits
1. data AW 0x00 + W: Lite bridge → Register block
2. data AW 0x04 + W: Lite bridge → Register block
3. data AW 0x08 + W: Lite bridge → Register block
4. data AW 0x0c + W: Lite bridge → Register block
One combined response
The third write hit the read-only STATUS register and got SLVERR. The bridge combines the four answers into one B, and an error is sticky: the manager sees SLVERR.
More context
With both SLVERR and DECERR, the first received wins.
Follow the calls, values and waits
1. return OKAY: Register block → Lite bridge
2. return OKAY: Register block → Lite bridge
3. return SLVERR: Register block → Lite bridge
4. return OKAY: Register block → Lite bridge
5. return SLVERR: Lite bridge → AXI manager

Read the diagram as text

AXI manager: issues a 4-beat write
Lite bridge: converts and combines
Register block: AXI4-Lite
DRAM: full AXI, bursts pass

AXI manager → Lite bridge: AW, W, B
Lite bridge → Register block: single transfers
Lite bridge → DRAM: untouched

Without conversion, the first burst stalls the system.

AXI3, AXI4, AXI5

The channels, the handshake and the burst arithmetic have not changed since AXI3. What changed is at the edges: burst length, write data interleaving, locking, the attributes, and how a channel is flow-controlled.

Feature	AXI3	AXI4	AXI5
Burst length	1 to 16 transfers, all types	INCR 1 to 256; FIXED and WRAP 1 to 16	as AXI4
Write data interleaving	allowed, with a WID on every write beat	removed: write data follows the order of the addresses, no WID	removed
AxLOCK	two bits: normal, exclusive, locked	one bit: normal or exclusive; locked transactions removed	one bit; atomic transactions added
Write response	may be given before the address is accepted by some subordinates	only after AWVALID, AWREADY, WVALID, WREADY and WLAST	as AXI4
AxQOS, AxREGION, xUSER	absent	added	kept; AxQOS gains VAxQOSACCEPT
Transport	VALID/READY	VALID/READY	VALID/READY or credited: CRDT from the receiver, VALID only while the sender holds a credit, no READY
Unique ID indicator	absent	absent	optional AxIDUNQ, so downstream components skip ordering for IDs with nothing in flight
Read data chunking	absent	absent	optional: 128-bit chunks of one transaction returned in any order
Protection of the wires	none	none	optional parity on every channel and poison on data
Security	AxPROT	AxPROT	AxPROT, or AxPAS with Root and Realm spaces (RME) and Memory Encryption Contexts
The Lite subset	none	AXI4-Lite: one transfer, no IDs, no exclusives	AXI5-Lite: one transfer, reordering across IDs permitted, Device Non-bufferable

The generations side by side; Issue L describes AXI5 and refers to earlier issues for the rest.

Three rows deserve a sentence each. Write data interleaving is why AXI3 benches need a WID; with it gone, a monitor pairs write beats with addresses in order, as the monitor of lesson P2.17 does. Locked transactions were removed because they shut everyone else out of the interconnect and wrecked QoS guarantees; exclusive access does the job without that. Credited transport changes the handshake itself. The receiver hands out up to 15 credits per resource plane; the sender spends one per VALID cycle and may not assert VALID without one. There is no READY to wait for.

AXI5-Lite keeps the Lite idea and relaxes one rule. Responses to requests with different IDs may return out of order, so a Lite block can sit beside reordering subordinates behind an AXI5 interconnect. The signals of this module are the AXI5 signals; the properties that switch the optional features on are listed in the specification's interface classes and signal matrix.

Where you will meet it

Register blocks are AXI4-Lite in most SoCs and APB in the rest, and the two look alike from software: one transfer, full width, strobes. Bridges from AXI to either follow the same conversion rules.

Asked in interviews: the AXI family

What does AXI4-Lite remove?
Bursts, IDs, exclusives and the attributes: no AxLEN, AxSIZE, AxBURST, AxLOCK, AxCACHE, WLAST, RLAST or EXOKAY. It keeps the handshakes, the strobes, AxPROT and the responses.
Can a full AXI manager drive a Lite subordinate directly?
Only if the system guarantees Lite-shaped transactions and the subordinate reflects IDs. Otherwise a bridge converts, or refuses with a compliant error.
How are the responses of a converted burst combined?
Into one response for the original transaction. Any error is sticky; with both SLVERR and DECERR present, the first received is used.
What is WID?
The write data ID of AXI3, which allowed write beats of different transactions to interleave. AXI4 removed it: write data follows the order of the addresses.
What is credited transport?
The AXI5 option where the receiver gives credits and the sender asserts VALID only while it holds one; there is no READY. A credit cannot be used in the cycle it is given.

Try it

Every transaction here is one transfer: the writes get their B one edge after the data beat, the reads get their one beat one edge after the address. The task library is the full-AXI one, so each call still carries a length, a size and a burst type. The block ignores all three, and the checker is content because each transaction really is one beat of four bytes.

Now break it. Change the last read to axi_read(0, 32'h0, 3, 2, INCR) and the block answers one beat with RLAST while the checker expects four: the rule rlast at edge 16. Change a write address to 32'h10 and the block answers DECERR, the address being outside its map. Write with size = 1 and strb becomes 0011: only two bytes of the register change.

RUNIcarus Verilog · in your browser

Edit the code, then run it

Expected: e3 AW id=0 addr=0x0 len=0 size=2 INCR e4 W beat 0 data=0x1 strb=1111 last=1 addr 0x0 lanes 0-3 e5 B id=0 OKAY e6 AW id=0 addr=0x4 len=0 size=2 INCR e7 W beat 0 data=0xcafef00d strb=1111 last=1 addr 0x4 lanes 0-3 e8 B id=0 OKAY e9 AR id=0 addr=0x4 len=0 size=2 INCR e10 R id=0 beat 0 data=0xcafef00d OKAY last addr 0x4 lanes 0-3 DATA reads back 0xcafef00d e11 AW id=0 addr=0x8 len=0 size=2 INCR e12 W beat 0 data=0xdeadbeef strb=1111 last=1 addr 0x8 lanes 0-3 e13 B id=0 SLVERR a write to STATUS gets SLVERR e14 AR id=0 addr=0xc len=0 size=2 INCR e15 R id=0 beat 0 data=0x4c495445 OKAY last addr 0xc lanes 0-3 ID reads 0x4c495445 0x00000 01 00 00 00 0d f0 fe ca 01 00 00 00 45 54 49 4c checker: 3 writes, 2 reads, 0 stalled edges, 0 rules broken

Read included file: axi_pkg.sv

`timescale 1ns/1ns
// axi_pkg.sv: the arithmetic of a burst (read-only).
// Every transfer n of a burst has an address and a set of byte lanes, computed from the start
// address, the burst length, the transfer size and the burst type exactly as the AXI specification
// defines them. The memory, the manager tasks and the checker all use these functions, so they
// never disagree about where a byte lands.
package axi_pkg;
  localparam logic [1:0] FIXED = 2'b00, INCR = 2'b01, WRAP = 2'b10;
  localparam logic [1:0] OKAY = 2'b00, EXOKAY = 2'b01, SLVERR = 2'b10, DECERR = 2'b11;

  function automatic string burst_name(input logic [1:0] b);
    case (b) FIXED: return "FIXED"; INCR: return "INCR"; WRAP: return "WRAP"; default: return "RESERVED"; endcase
  endfunction
  function automatic string resp_name(input logic [1:0] r);
    case (r) OKAY: return "OKAY"; EXOKAY: return "EXOKAY"; SLVERR: return "SLVERR"; default: return "DECERR"; endcase
  endfunction

  // Bytes in one transfer: 1, 2, 4, ... 128.
  function automatic int bytes_of(input logic [2:0] size);
    return 1 << size;
  endfunction

  // The address of transfer n (n counts from 0).
  //   transfer 0 uses the start address as given, aligned or not;
  //   later transfers use the start address aligned down to the transfer size, plus n transfers;
  //   a WRAP burst returns to its wrap boundary (the start aligned down to the whole burst) when
  //   it reaches the end of that window; a FIXED burst repeats the start address.
  function automatic int unsigned beat_addr(input int unsigned start, input int len, input logic [2:0] size,
                                            input logic [1:0] burst, input int n);
    int unsigned nb = 1 << size;
    int unsigned aligned = (start / nb) * nb;
    int unsigned window = nb * (len + 1);
    int unsigned boundary = (start / window) * window;
    int unsigned a;
    if (burst == FIXED || n == 0) return start;
    a = aligned + n * nb;
    if (burst == WRAP && a >= boundary + window) a = a - window;
    return a;
  endfunction

  // The byte lanes transfer n uses on a bus of bus_bytes bytes, packed as {upper, lower}.
  // Transfer 0 of an unaligned burst (and every transfer of a FIXED burst) uses only the lanes from
  // its address up to the end of its aligned transfer; every other transfer uses all the lanes of
  // its size.
  function automatic logic [15:0] beat_lanes(input int unsigned start, input int len, input logic [2:0] size,
                                             input logic [1:0] burst, input int n, input int bus_bytes);
    int unsigned nb = 1 << size;
    int unsigned a = beat_addr(start, len, size, burst, n);
    int unsigned aligned = (a / nb) * nb;
    int unsigned word = (a / bus_bytes) * bus_bytes;
    int lower = a - word;
    int upper = (n == 0 || burst == FIXED) ? (aligned + nb - 1 - word) : (lower + nb - 1);
    return {upper[7:0], lower[7:0]};
  endfunction

  // The strobe of transfer n: a 1 for every lane it uses (bit l is lane l).
  function automatic logic [63:0] beat_strb(input int unsigned start, input int len, input logic [2:0] size,
                                            input logic [1:0] burst, input int n, input int bus_bytes);
    logic [15:0] lanes = beat_lanes(start, len, size, burst, n, bus_bytes);
    logic [63:0] s = 0;
    for (int l = lanes[7:0]; l <= lanes[15:8]; l++) s[l] = 1'b1;
    return s;
  endfunction

  // True when the burst crosses a 4 KB boundary (only an INCR burst can).
  function automatic bit crosses_4k(input int unsigned start, input int len, input logic [2:0] size, input logic [1:0] burst);
    if (burst != INCR) return 0;
    return (beat_addr(start, len, size, burst, 0) / 4096) != ((beat_addr(start, len, size, burst, len) + (1 << size) - 1) / 4096);
  endfunction
endpackage

Read included file: axi_mem.sv

`timescale 1ns/1ns
// axi_mem.sv: an AXI4 subordinate with a byte-addressed memory behind it (read-only in this lesson).
// It accepts requests on AW and AR, write beats on W (before or after their AW), writes the bytes a
// burst addresses using the strobes, and answers on B and R after a latency. The switches below are
// plain variables: the stimulus sets them by name (mem.reorder = 1;) before it starts.
//   rd_latency, wr_latency   cycles from a request (or its last write beat) to its first response
//   slow_latency, slow_above addresses at or above slow_above answer after slow_latency instead
//   err_above                addresses at or above err_above get SLVERR (and are not written)
//   reorder                  answer transactions with DIFFERENT IDs as soon as each is ready;
//                            transactions with the same ID still answer in order
//   interleave               interleave the read data beats of ready transactions with different IDs
//   excl_on                  support exclusive access (one monitor per ID), else answer OKAY
//   posted                   apply a write to the memory only when its response is sent, so a read
//                            that arrives between the last beat and B still sees the old bytes
//   trace                    print every byte the memory writes
// Broken twins, each off by default: early_b (B before the last write beat and before AW),
// ignore_strobes (write every lane of the bus word), drop_hold (RDATA changes while RVALID waits
// for RREADY), reorder_same_id (a later transaction with the same ID may answer first),
// wrap_bug (a WRAP burst addressed like INCR).
module axi_mem #(parameter int DATA_W = 32, parameter int ID_W = 4, parameter int DEPTH = 65536) (
  input  logic              aclk,
  input  logic              aresetn,
  input  logic [ID_W-1:0]   awid,
  input  logic [31:0]       awaddr,
  input  logic [7:0]        awlen,
  input  logic [2:0]        awsize,
  input  logic [1:0]        awburst,
  input  logic              awlock,
  input  logic [3:0]        awcache,
  input  logic [2:0]        awprot,
  input  logic              awvalid,
  output logic              awready,
  input  logic [DATA_W-1:0] wdata,
  input  logic [DATA_W/8-1:0] wstrb,
  input  logic              wlast,
  input  logic              wvalid,
  output logic              wready,
  output logic [ID_W-1:0]   bid,
  output logic [1:0]        bresp,
  output logic              bvalid,
  input  logic              bready,
  input  logic [ID_W-1:0]   arid,
  input  logic [31:0]       araddr,
  input  logic [7:0]        arlen,
  input  logic [2:0]        arsize,
  input  logic [1:0]        arburst,
  input  logic              arlock,
  input  logic [3:0]        arcache,
  input  logic [2:0]        arprot,
  input  logic              arvalid,
  output logic              arready,
  output logic [ID_W-1:0]   rid,
  output logic [DATA_W-1:0] rdata,
  output logic [1:0]        rresp,
  output logic              rlast,
  output logic              rvalid,
  input  logic              rready
);
  import axi_pkg::*;
  localparam int BUS = DATA_W / 8;
  localparam int N = 16;                      // transactions in flight per direction

  // ---- switches ----
  int rd_latency = 2, wr_latency = 2, slow_latency = 8;
  int unsigned slow_above = 32'hffff_ffff, err_above = 32'hffff_ffff;
  bit reorder = 0, interleave = 0, excl_on = 0, posted = 0, trace = 0;
  bit early_b = 0, ignore_strobes = 0, drop_hold = 0, reorder_same_id = 0, wrap_bug = 0;

  // ---- the memory ----
  logic [7:0] mem [0:DEPTH-1];
  initial for (int i = 0; i < DEPTH; i++) mem[i] = 8'h00;

  int cycle = -1;
  int seq = 0;                                // every request gets a sequence number: issue order

  // ---- write side: accepted AW requests (a ring) and write beats (a ring) ----
  logic [ID_W-1:0] aw_id [0:N-1];
  int unsigned     aw_addr [0:N-1];
  int              aw_len [0:N-1];
  logic [2:0]      aw_size [0:N-1];
  logic [1:0]      aw_burst [0:N-1];
  logic            aw_lock [0:N-1];
  int aw_head = 0, aw_tail = 0, aw_count = 0;
  localparam int WQ = 1024;
  logic [DATA_W-1:0] w_data [0:WQ-1];
  logic [BUS-1:0]    w_strb [0:WQ-1];
  logic              w_last [0:WQ-1];
  int w_head = 0, w_tail = 0, w_count = 0, w_bursts = 0;   // w_bursts: complete bursts in the ring

  // ---- write responses waiting for their latency ----
  logic            b_use [0:N-1];
  logic [ID_W-1:0] b_id [0:N-1];
  logic [1:0]      b_rsp [0:N-1];
  int              b_at [0:N-1], b_seq [0:N-1];
  logic            b_driving = 0;
  logic            early_done = 0;            // the early_b twin answers once per burst
  // posted writes: the beats of a write kept until its response goes out
  logic [DATA_W-1:0] p_data [0:N-1][0:255];
  logic [BUS-1:0]    p_strb [0:N-1][0:255];
  int unsigned       p_addr [0:N-1];
  int                p_len [0:N-1];
  logic [2:0]        p_size [0:N-1];
  logic [1:0]        p_burst [0:N-1];
  logic              p_pending [0:N-1];

  // ---- read side: accepted AR requests with their progress ----
  logic            r_use [0:N-1];
  logic [ID_W-1:0] r_id [0:N-1];
  int unsigned     r_addr [0:N-1];
  int              r_len [0:N-1];
  logic [2:0]      r_size [0:N-1];
  logic [1:0]      r_burst [0:N-1];
  logic            r_lock [0:N-1];
  int              r_at [0:N-1], r_seq [0:N-1], r_beat [0:N-1], r_served [0:N-1];
  int              r_cur = -1;                // the transaction whose beat is on the wires
  logic            r_driving = 0;

  // ---- exclusive monitors, one per ID ----
  logic        mon_use [0:(1<<ID_W)-1];
  int unsigned mon_addr [0:(1<<ID_W)-1];
  int unsigned mon_bytes [0:(1<<ID_W)-1];

  initial begin
    for (int i = 0; i < N; i++) begin b_use[i] = 0; r_use[i] = 0; p_pending[i] = 0; end
    for (int i = 0; i < (1 << ID_W); i++) mon_use[i] = 0;
    awready = 0; wready = 0; arready = 0; bvalid = 0; rvalid = 0; bid = 0; bresp = 0; rid = 0; rresp = 0; rlast = 0; rdata = 0;
  end

  function automatic int latency_of(input int unsigned a, input int base);
    return (a >= slow_above) ? slow_latency : base;
  endfunction
  function automatic logic [1:0] burst_used(input logic [1:0] b);
    return (wrap_bug && b == WRAP) ? INCR : b;
  endfunction

  // ---- selection policies ----
  // The oldest of all pending entries, or the oldest of its ID: the in-order rule of the protocol.
  function automatic bit b_oldest(input int i, input bit same_id_only);
    for (int j = 0; j < N; j++)
      if (b_use[j] && j != i && b_seq[j] < b_seq[i] && (!same_id_only || b_id[j] == b_id[i])) return 0;
    return 1;
  endfunction
  function automatic bit r_oldest(input int i, input bit same_id_only);
    for (int j = 0; j < N; j++)
      if (r_use[j] && j != i && r_seq[j] < r_seq[i] && (!same_id_only || r_id[j] == r_id[i])) return 0;
    return 1;
  endfunction
  function automatic bit b_eligible(input int i);
    if (!b_use[i] || b_at[i] > cycle) return 0;
    if (!reorder) return b_oldest(i, 0);
    return reorder_same_id ? 1 : b_oldest(i, 1);
  endfunction
  function automatic bit r_eligible(input int i);
    if (!r_use[i] || r_at[i] > cycle) return 0;
    if (!reorder) return r_oldest(i, 0);
    return reorder_same_id ? 1 : r_oldest(i, 1);
  endfunction
  function automatic int free_b();
    for (int i = 0; i < N; i++) if (!b_use[i]) return i;
    return -1;
  endfunction
  function automatic int free_r();
    for (int i = 0; i < N; i++) if (!r_use[i]) return i;
    return -1;
  endfunction
  function automatic int pick_b();
    int best = -1;
    for (int i = 0; i < N; i++) if (b_eligible(i) && (best < 0 || b_seq[i] < b_seq[best])) best = i;
    return best;
  endfunction
  function automatic int pick_r();
    int best = -1;
    for (int i = 0; i < N; i++) if (r_eligible(i)) begin
      if (best < 0) best = i;
      else if (interleave ? (r_served[i] < r_served[best]) : (r_seq[i] < r_seq[best])) best = i;
    end
    return best;
  endfunction

  // ---- the bytes of one read beat, as the bus word that holds them ----
  function automatic logic [DATA_W-1:0] read_word(input int unsigned a);
    logic [DATA_W-1:0] d = 0;
    int unsigned word = (a / BUS) * BUS;
    for (int l = 0; l < BUS; l++) d[8*l +: 8] = (word + l < DEPTH) ? mem[word + l] : 8'h00;
    return d;
  endfunction

  // ---- the write of one complete burst into the memory ----
  task automatic write_burst(input int e);
    logic [1:0]  rsp = OKAY;
    logic        do_write = 1, ended = 0;
    int unsigned a, word;
    logic [15:0] lanes;
    int          n = 0, slot;
    int unsigned total = (1 << aw_size[e]) * (aw_len[e] + 1);
    slot = free_b();
    if (aw_lock[e] && excl_on) begin
      if (mon_use[aw_id[e]] && mon_addr[aw_id[e]] == aw_addr[e]) begin
        rsp = EXOKAY;
        $display("mem e%0d: exclusive write id=%0d at 0x%0h: the monitor matched, EXOKAY", cycle, aw_id[e], aw_addr[e]);
      end else begin
        do_write = 0;
        $display("mem e%0d: exclusive write id=%0d at 0x%0h: no monitor, OKAY and nothing written", cycle, aw_id[e], aw_addr[e]);
      end
    end
    while (!ended && n <= aw_len[e]) begin
      a = beat_addr(aw_addr[e], aw_len[e], aw_size[e], burst_used(aw_burst[e]), n);
      lanes = beat_lanes(aw_addr[e], aw_len[e], aw_size[e], burst_used(aw_burst[e]), n, BUS);
      word = (a / BUS) * BUS;
      if (a >= err_above) rsp = SLVERR;
      else if (do_write && posted && slot >= 0) begin
        p_data[slot][n] = w_data[w_head]; p_strb[slot][n] = w_strb[w_head];
      end else if (do_write) begin
        for (int l = 0; l < BUS; l++)
          if ((w_strb[w_head][l] || ignore_strobes) && word + l < DEPTH) begin
            mem[word + l] = w_data[w_head][8*l +: 8];
            if (trace) $display("mem e%0d: beat %0d writes 0x%02h to 0x%0h (lane %0d)", cycle, n, w_data[w_head][8*l +: 8], word + l, l);
          end
      end
      ended = w_last[w_head];                      // a burst ends at its WLAST, whatever AWLEN said
      w_head = (w_head + 1) % WQ; w_count = w_count - 1;
      n = n + 1;
    end
    while (!ended) begin                           // beats past AWLEN (a broken manager) are dropped
      ended = w_last[w_head];
      w_head = (w_head + 1) % WQ; w_count = w_count - 1;
    end
    // A write clears every monitor that watches a byte it touched.
    if (do_write)
      for (int i = 0; i < (1 << ID_W); i++)
        if (mon_use[i] && mon_addr[i] < aw_addr[e] + total && aw_addr[e] < mon_addr[i] + mon_bytes[i]) mon_use[i] = 0;
    if (slot >= 0) begin
      b_use[slot] = 1; b_id[slot] = aw_id[e]; b_rsp[slot] = rsp; b_seq[slot] = seq; seq = seq + 1;
      b_at[slot] = cycle + latency_of(aw_addr[e], wr_latency);
      if (posted && do_write) begin
        p_pending[slot] = 1; p_addr[slot] = aw_addr[e]; p_len[slot] = n - 1; p_size[slot] = aw_size[e]; p_burst[slot] = aw_burst[e];
      end
    end
  endtask

  // A posted write reaches the memory when its response goes out.
  task automatic apply_posted(input int i);
    int unsigned a, word;
    for (int n = 0; n <= p_len[i]; n++) begin
      a = beat_addr(p_addr[i], p_len[i], p_size[i], burst_used(p_burst[i]), n);
      word = (a / BUS) * BUS;
      if (a < err_above)
        for (int l = 0; l < BUS; l++)
          if ((p_strb[i][n][l] || ignore_strobes) && word + l < DEPTH) begin
            mem[word + l] = p_data[i][n][8*l +: 8];
            if (trace) $display("mem e%0d: posted beat %0d writes 0x%02h to 0x%0h (lane %0d)", cycle, n, p_data[i][n][8*l +: 8], word + l, l);
          end
    end
    p_pending[i] = 0;
  endtask

  int pick, extra;
  always @(posedge aclk) begin
    cycle = cycle + 1;
    if (!aresetn) begin
      aw_head = 0; aw_tail = 0; aw_count = 0; w_head = 0; w_tail = 0; w_count = 0; w_bursts = 0;
      for (int i = 0; i < N; i++) begin b_use[i] = 0; r_use[i] = 0; end
      b_driving = 0; r_driving = 0; r_cur = -1;
      awready <= 0; wready <= 0; arready <= 0; bvalid <= 0; rvalid <= 0;
    end else begin
      // -- AW: take a request while there is room --
      if (awvalid && awready) begin
        aw_id[aw_tail] = awid; aw_addr[aw_tail] = awaddr; aw_len[aw_tail] = awlen; aw_size[aw_tail] = awsize;
        aw_burst[aw_tail] = awburst; aw_lock[aw_tail] = awlock;
        aw_tail = (aw_tail + 1) % N; aw_count = aw_count + 1;
      end
      // -- W: take a beat while there is room --
      if (wvalid && wready) begin
        w_data[w_tail] = wdata; w_strb[w_tail] = wstrb; w_last[w_tail] = wlast;
        w_tail = (w_tail + 1) % WQ; w_count = w_count + 1;
        if (wlast) w_bursts = w_bursts + 1;
      end
      // -- a complete burst with its request: write it and schedule B --
      if (aw_count > 0 && w_bursts > 0) begin
        write_burst(aw_head);
        aw_head = (aw_head + 1) % N; aw_count = aw_count - 1; w_bursts = w_bursts - 1;
        early_done = 0;
      end else if (early_b && !early_done && w_count > 0 && w_bursts == 0) begin
        // The broken twin: a response as soon as the first write beat arrived, before WLAST and,
        // when the data came first, before the address.
        pick = free_b();
        if (pick >= 0) begin
          b_use[pick] = 1; b_id[pick] = (aw_count > 0) ? aw_id[aw_head] : awid; b_rsp[pick] = OKAY; b_seq[pick] = seq; seq = seq + 1; b_at[pick] = cycle;
          early_done = 1;
        end
      end
      // -- B: finish a handshake, then put the next response on the wires --
      if (b_driving && bready) b_driving = 0;
      if (!b_driving) begin
        pick = pick_b();
        if (pick >= 0) begin
          if (p_pending[pick]) apply_posted(pick);
          b_driving = 1; bid <= b_id[pick]; bresp <= b_rsp[pick]; b_use[pick] = 0;
        end
      end
      bvalid <= b_driving;
      // -- AR: take a request while there is room --
      if (arvalid && arready) begin
        pick = free_r();
        if (pick >= 0) begin
          r_use[pick] = 1; r_id[pick] = arid; r_addr[pick] = araddr; r_len[pick] = arlen; r_size[pick] = arsize; r_burst[pick] = arburst;
          r_lock[pick] = arlock; r_beat[pick] = 0; r_seq[pick] = seq; seq = seq + 1; r_served[pick] = -1;
          r_at[pick] = cycle + latency_of(araddr, rd_latency);
          if (arlock && excl_on) begin
            mon_use[arid] = 1; mon_addr[arid] = araddr; mon_bytes[arid] = (1 << arsize) * (arlen + 1);
            $display("mem e%0d: exclusive read id=%0d at 0x%0h: monitor set", cycle, arid, araddr);
          end
        end
      end
      // -- R: finish a handshake, then put the next beat on the wires --
      if (r_driving && !rready && drop_hold) rdata <= rdata + 1;   // the broken twin: data not held
      if (r_driving && rready) begin
        r_driving = 0;
        if (r_beat[r_cur] > r_len[r_cur]) begin r_use[r_cur] = 0; r_cur = -1; end
        else if (interleave) r_cur = -1;
      end
      if (!r_driving) begin
        pick = (r_cur >= 0) ? r_cur : pick_r();
        if (pick >= 0) begin
          r_cur = pick; r_driving = 1; r_served[pick] = cycle;
          extra = r_beat[pick];
          rid <= r_id[pick];
          rdata <= read_word(beat_addr(r_addr[pick], r_len[pick], r_size[pick], burst_used(r_burst[pick]), extra));
          rresp <= (beat_addr(r_addr[pick], r_len[pick], r_size[pick], burst_used(r_burst[pick]), extra) >= err_above) ? SLVERR
                 : ((r_lock[pick] && excl_on) ? EXOKAY : OKAY);
          rlast <= (extra == r_len[pick]);
          r_beat[pick] = extra + 1;
        end
      end
      rvalid <= r_driving;
      awready <= (aw_count < N - 1);
      wready  <= (w_count < WQ - 2);
      arready <= 1;
    end
  end
endmodule

Read included file: axi_checker.sv

`timescale 1ns/1ns
// axi_checker.sv: the rules of an AXI4 interface, checked at every rising edge (read-only).
// Each broken rule is named with the channel and the edge where it was seen:
//   reset      a VALID is 1 while reset is active;
//   hold       a VALID dropped before its READY: the offer was withdrawn;
//   stable     a channel's payload changed while its offer waited;
//   known      a payload is x while its VALID is 1;
//   len        a FIXED or WRAP burst longer than 16 beats;
//   wrap       a WRAP burst whose length is not 2, 4, 8 or 16 beats or whose address is not aligned;
//   boundary   a burst that crosses a 4 KB boundary;
//   size       a transfer wider than the data bus;
//   strobe     a write strobe on a lane the beat does not address;
//   wlast      WLAST on the wrong beat (not AWLEN), or missing after it;
//   rlast      RLAST on the wrong beat of the oldest read with that ID, or missing after it;
//   border     BVALID before any outstanding write has its last beat, or before its AW;
//   bid, rid   a response ID with no outstanding request of that ID;
//   exokay     EXOKAY for a request that was not exclusive;
//   exclusive  an exclusive request whose bytes are not a power of two up to 128, or not aligned to them.
// The rules no checker can see on the wires (VALID must not wait for READY; same-ID responses
// in the order of their requests) are checked by the data the tasks compare (lessons P2.2, P2.10).
module axi_checker #(parameter int DATA_W = 32, parameter int ID_W = 4) (
  input logic              aclk,
  input logic              aresetn,
  input logic [ID_W-1:0]   awid,
  input logic [31:0]       awaddr,
  input logic [7:0]        awlen,
  input logic [2:0]        awsize,
  input logic [1:0]        awburst,
  input logic              awlock,
  input logic              awvalid,
  input logic              awready,
  input logic [DATA_W-1:0] wdata,
  input logic [DATA_W/8-1:0] wstrb,
  input logic              wlast,
  input logic              wvalid,
  input logic              wready,
  input logic [ID_W-1:0]   bid,
  input logic [1:0]        bresp,
  input logic              bvalid,
  input logic              bready,
  input logic [ID_W-1:0]   arid,
  input logic [31:0]       araddr,
  input logic [7:0]        arlen,
  input logic [2:0]        arsize,
  input logic [1:0]        arburst,
  input logic              arlock,
  input logic              arvalid,
  input logic              arready,
  input logic [ID_W-1:0]   rid,
  input logic [DATA_W-1:0] rdata,
  input logic [1:0]        rresp,
  input logic              rlast,
  input logic              rvalid,
  input logic              rready
);
  import axi_pkg::*;
  localparam int BUS = DATA_W / 8;
  localparam int Q = 64;
  int cycle = -1, writes = 0, reads = 0, stalls = 0, broken = 0;
  logic [DATA_W-1:0] used;

  function void report(input string rule, input string what);
    broken++;
    $display("RULE %s broken at edge %0d: %s", rule, cycle, what);
  endfunction

  // Previous values of every channel, for hold and stable.
  logic p_awv = 0, p_awr = 0, p_wv = 0, p_wr = 0, p_bv = 0, p_br = 0, p_arv = 0, p_arr = 0, p_rv = 0, p_rr = 0;
  logic [31:0] p_awaddr, p_araddr;
  logic [7:0] p_awlen, p_arlen;
  logic [2:0] p_awsize, p_arsize;
  logic [1:0] p_awburst, p_arburst, p_bresp, p_rresp;
  logic [ID_W-1:0] p_awid, p_arid, p_bid, p_rid;
  logic [DATA_W-1:0] p_wdata, p_rdata;
  logic [BUS-1:0] p_wstrb;
  logic p_wlast, p_rlast, p_awlock, p_arlock;

  // Write requests in order (AXI4 write data follows the order of the addresses).
  int unsigned q_addr [0:Q-1];
  int q_len [0:Q-1];
  logic [2:0] q_size [0:Q-1];
  logic [1:0] q_burst [0:Q-1];
  int aw_n = 0;                 // requests accepted
  int wb_n = 0;                 // write bursts started
  int wb_done = 0;              // write bursts ended (WLAST seen)
  int w_beat = 0;               // beats so far in the current burst
  int b_n = 0;                  // responses given
  // Beats recorded for bursts that ran ahead of their AW: strobes and count, checked when AW arrives.
  logic [BUS-1:0] rec_strb [0:Q-1][0:255];
  int rec_beats [0:Q-1];
  logic rec_open [0:Q-1];
  // Outstanding requests per ID, and the read requests per ID in order.
  int aw_out [0:(1<<ID_W)-1], ar_out [0:(1<<ID_W)-1], aw_excl [0:(1<<ID_W)-1], ar_excl [0:(1<<ID_W)-1];
  int rq_len [0:(1<<ID_W)-1][0:15];
  int rq_head [0:(1<<ID_W)-1], rq_tail [0:(1<<ID_W)-1], r_beat [0:(1<<ID_W)-1];
  initial for (int i = 0; i < (1 << ID_W); i++) begin aw_out[i] = 0; ar_out[i] = 0; aw_excl[i] = 0; ar_excl[i] = 0; rq_head[i] = 0; rq_tail[i] = 0; r_beat[i] = 0; end
  initial for (int i = 0; i < Q; i++) begin rec_beats[i] = 0; rec_open[i] = 0; end

  function automatic bit pow2_le128(input int unsigned n);
    return (n == 1 || n == 2 || n == 4 || n == 8 || n == 16 || n == 32 || n == 64 || n == 128);
  endfunction

  task automatic check_request(input string ch, input int unsigned addr, input int len, input logic [2:0] size, input logic [1:0] burst, input logic lock);
    int unsigned bytes = (1 << size) * (len + 1);
    if ((burst == FIXED || burst == WRAP) && len > 15) report("len", $sformatf("%s: a %s burst of %0d beats (16 at most)", ch, burst_name(burst), len + 1));
    if (burst == WRAP && !(len == 1 || len == 3 || len == 7 || len == 15)) report("wrap", $sformatf("%s: a WRAP burst of %0d beats (2, 4, 8 or 16)", ch, len + 1));
    if (burst == WRAP && (addr % (1 << size)) != 0) report("wrap", $sformatf("%s: WRAP burst at 0x%0h is not aligned to its %0d-byte transfers", ch, addr, 1 << size));
    if (burst == 2'b11) report("len", $sformatf("%s: burst type 2'b11 is reserved", ch));
    if ((1 << size) > BUS) report("size", $sformatf("%s: %0d-byte transfers on a %0d-byte bus", ch, 1 << size, BUS));
    if (crosses_4k(addr, len, size, burst)) report("boundary", $sformatf("%s: burst at 0x%0h, %0d beats of %0d bytes, crosses a 4 KB boundary", ch, addr, len + 1, 1 << size));
    if (lock && (!pow2_le128(bytes) || (addr % bytes) != 0)) report("exclusive", $sformatf("%s: exclusive access of %0d bytes at 0x%0h (a power of two up to 128, aligned)", ch, bytes, addr));
  endtask

  task automatic check_strobe(input int k, input int n, input logic [BUS-1:0] strb);
    logic [63:0] allowed = beat_strb(q_addr[k % Q], q_len[k % Q], q_size[k % Q], q_burst[k % Q], n, BUS);
    if ((strb & ~allowed[BUS-1:0]) != 0)
      report("strobe", $sformatf("W beat %0d of write %0d: strobe %b on lanes outside %b", n, k, strb, allowed[BUS-1:0]));
  endtask

  always @(posedge aclk) begin
    cycle++;
    if (!aresetn) begin
      if (awvalid === 1 || wvalid === 1 || arvalid === 1) report("reset", "a manager VALID is 1 during reset");
      if (bvalid === 1 || rvalid === 1) report("reset", "a subordinate VALID is 1 during reset");
    end else begin
      // hold, stable and known, per channel
      if (p_awv && !p_awr && awvalid !== 1) report("hold", "AWVALID dropped before AWREADY");
      if (p_awv && !p_awr && awvalid === 1 && (awaddr !== p_awaddr || awlen !== p_awlen || awsize !== p_awsize || awburst !== p_awburst || awid !== p_awid || awlock !== p_awlock)) report("stable", "AW payload changed while the request waited");
      if (p_wv && !p_wr && wvalid !== 1) report("hold", "WVALID dropped before WREADY");
      if (p_wv && !p_wr && wvalid === 1 && (wdata !== p_wdata || wstrb !== p_wstrb || wlast !== p_wlast)) report("stable", "W payload changed while the beat waited");
      if (p_bv && !p_br && bvalid !== 1) report("hold", "BVALID dropped before BREADY");
      if (p_bv && !p_br && bvalid === 1 && (bresp !== p_bresp || bid !== p_bid)) report("stable", "B payload changed while the response waited");
      if (p_arv && !p_arr && arvalid !== 1) report("hold", "ARVALID dropped before ARREADY");
      if (p_arv && !p_arr && arvalid === 1 && (araddr !== p_araddr || arlen !== p_arlen || arsize !== p_arsize || arburst !== p_arburst || arid !== p_arid || arlock !== p_arlock)) report("stable", "AR payload changed while the request waited");
      if (p_rv && !p_rr && rvalid !== 1) report("hold", "RVALID dropped before RREADY");
      if (p_rv && !p_rr && rvalid === 1 && (rdata !== p_rdata || rresp !== p_rresp || rid !== p_rid || rlast !== p_rlast)) report("stable", "R payload changed while the beat waited");
      if (awvalid === 1 && ($isunknown(awaddr) || $isunknown(awlen) || $isunknown(awsize) || $isunknown(awburst) || $isunknown(awid))) report("known", "AW payload is x while AWVALID is 1");
      if (wvalid === 1 && ($isunknown(wstrb) || $isunknown(wlast))) report("known", "W strobe or last is x while WVALID is 1");
      else if (wvalid === 1) begin
        used = '0;
        for (int l = 0; l < BUS; l++) if (wstrb[l] === 1) used[8*l +: 8] = 8'hff;
        if ($isunknown(wdata & used)) report("known", "W data is x on a strobed lane while WVALID is 1");
      end
      if (arvalid === 1 && ($isunknown(araddr) || $isunknown(arlen) || $isunknown(arsize) || $isunknown(arburst) || $isunknown(arid))) report("known", "AR payload is x while ARVALID is 1");
      if (bvalid === 1 && ($isunknown(bresp) || $isunknown(bid))) report("known", "B payload is x while BVALID is 1");
      if (rvalid === 1 && ($isunknown(rresp) || $isunknown(rid) || $isunknown(rlast))) report("known", "R payload is x while RVALID is 1");
      if ((awvalid === 1 && awready !== 1) || (wvalid === 1 && wready !== 1) || (arvalid === 1 && arready !== 1) ||
          (bvalid === 1 && bready !== 1) || (rvalid === 1 && rready !== 1)) stalls++;
      // AW accepted
      if (awvalid === 1 && awready === 1) begin
        check_request("AW", awaddr, awlen, awsize, awburst, awlock);
        q_addr[aw_n % Q] = awaddr; q_len[aw_n % Q] = awlen; q_size[aw_n % Q] = awsize; q_burst[aw_n % Q] = awburst;
        aw_out[awid]++; if (awlock) aw_excl[awid]++;
        // beats of this write that arrived before its address: check them now
        if (rec_beats[aw_n % Q] > 0) begin
          for (int n = 0; n < rec_beats[aw_n % Q]; n++) check_strobe(aw_n, n, rec_strb[aw_n % Q][n]);
          if (!rec_open[aw_n % Q] && rec_beats[aw_n % Q] != awlen + 1)
            report("wlast", $sformatf("write %0d sent %0d beats before its AW said AWLEN=%0d", aw_n, rec_beats[aw_n % Q], awlen));
          if (!rec_open[aw_n % Q]) rec_beats[aw_n % Q] = 0;
        end
        aw_n++;
      end
      // W beat accepted
      if (wvalid === 1 && wready === 1) begin
        if (w_beat == 0) begin wb_n++; rec_beats[(wb_n - 1) % Q] = 0; rec_open[(wb_n - 1) % Q] = 1; end
        if (wb_n <= aw_n) begin
          check_strobe(wb_n - 1, w_beat, wstrb);
          if (wlast === 1 && w_beat != q_len[(wb_n - 1) % Q]) report("wlast", $sformatf("WLAST on beat %0d of write %0d, AWLEN=%0d", w_beat, wb_n - 1, q_len[(wb_n - 1) % Q]));
          if (wlast !== 1 && w_beat == q_len[(wb_n - 1) % Q]) report("wlast", $sformatf("beat %0d of write %0d is AWLEN=%0d but WLAST is 0", w_beat, wb_n - 1, q_len[(wb_n - 1) % Q]));
        end else begin
          rec_strb[(wb_n - 1) % Q][w_beat] = wstrb;
        end
        rec_beats[(wb_n - 1) % Q] = w_beat + 1;
        w_beat++;
        if (wlast === 1) begin w_beat = 0; wb_done++; rec_open[(wb_n - 1) % Q] = 0; if (wb_n <= aw_n) rec_beats[(wb_n - 1) % Q] = 0; end
      end
      // B offered or accepted
      if (bvalid === 1 && !p_bv) begin
        if (b_n >= aw_n && b_n >= wb_done) report("border", "BVALID with no write to answer: neither an AW nor a WLAST is outstanding");
        else if (b_n >= wb_done) report("border", "BVALID before the last beat of the write it answers");
        else if (b_n >= aw_n) report("border", "BVALID before the AW of the write it answers was accepted");
      end
      if (bvalid === 1 && bready === 1) begin
        if (aw_out[bid] == 0) report("bid", $sformatf("B with id %0d, which has no outstanding write", bid));
        else begin
          aw_out[bid]--; writes++;
          if (bresp === EXOKAY && aw_excl[bid] == 0) report("exokay", $sformatf("EXOKAY for write id %0d, which was not exclusive", bid));
          if (aw_excl[bid] > 0 && aw_excl[bid] > aw_out[bid]) aw_excl[bid] = aw_out[bid];
        end
        b_n++;
      end
      // AR accepted
      if (arvalid === 1 && arready === 1) begin
        check_request("AR", araddr, arlen, arsize, arburst, arlock);
        rq_len[arid][rq_tail[arid]] = arlen; rq_tail[arid] = (rq_tail[arid] + 1) % 16;
        ar_out[arid]++; if (arlock) ar_excl[arid]++;
      end
      // R beat accepted
      if (rvalid === 1 && rready === 1) begin
        if (ar_out[rid] == 0) report("rid", $sformatf("R with id %0d, which has no outstanding read", rid));
        else begin
          if (rlast === 1 && r_beat[rid] != rq_len[rid][rq_head[rid]])
            report("rlast", $sformatf("RLAST on beat %0d of the oldest read with id %0d, whose ARLEN is %0d", r_beat[rid], rid, rq_len[rid][rq_head[rid]]));
          if (rlast !== 1 && r_beat[rid] == rq_len[rid][rq_head[rid]])
            report("rlast", $sformatf("beat %0d of the oldest read with id %0d is its ARLEN but RLAST is 0", r_beat[rid], rid));
          if (rresp === EXOKAY && ar_excl[rid] == 0) report("exokay", $sformatf("EXOKAY for read id %0d, which was not exclusive", rid));
          r_beat[rid]++;
          if (rlast === 1) begin
            r_beat[rid] = 0; rq_head[rid] = (rq_head[rid] + 1) % 16; ar_out[rid]--; reads++;
            if (ar_excl[rid] > ar_out[rid]) ar_excl[rid] = ar_out[rid];
          end
        end
      end
    end
    p_awv = (awvalid === 1); p_awr = (awready === 1); p_wv = (wvalid === 1); p_wr = (wready === 1);
    p_bv = (bvalid === 1); p_br = (bready === 1); p_arv = (arvalid === 1); p_arr = (arready === 1);
    p_rv = (rvalid === 1); p_rr = (rready === 1);
    p_awaddr = awaddr; p_awlen = awlen; p_awsize = awsize; p_awburst = awburst; p_awid = awid; p_awlock = awlock;
    p_wdata = wdata; p_wstrb = wstrb; p_wlast = wlast; p_bresp = bresp; p_bid = bid;
    p_araddr = araddr; p_arlen = arlen; p_arsize = arsize; p_arburst = arburst; p_arid = arid; p_arlock = arlock;
    p_rdata = rdata; p_rresp = rresp; p_rid = rid; p_rlast = rlast;
  end
  final $display("checker: %0d writes, %0d reads, %0d stalled edges, %0d rules broken", writes, reads, stalls, broken);
endmodule

Read included file: axi_tasks.svh

// axi_tasks.svh: the manager side of the bench, as tasks for the stimulus (read-only).
// Data for a write burst goes in wd[0], wd[1], ... (one entry per beat, the lowest byte at the
// lowest address); the data of a read comes back in rd[0], rd[1], ... with its responses in rr[].
// Every task prints the beat log: one line per handshake, with the edge where it happened.
// `cycle` counts rising edges from 0.
int cycle = -1;
always @(posedge aclk) cycle = cycle + 1;

logic [63:0] wd [0:255];
logic [63:0] rd [0:255];
logic [1:0]  rr [0:255];
logic [63:0] rdq [0:15][0:255];     // read data per ID, for reads collected out of order
logic [1:0]  rrq [0:15][0:255];
int          rdn [0:15];            // beats received per ID
logic [1:0]  last_bresp = 0;
int          last_beats = 0;
// What the task is driving right now, for the waveform scenes: the address and lanes of the beat.
int unsigned beat_a = 0;
logic [7:0]  beat_m = 0;
// quiet = 1 silences the beat log (a predict item can then ask for a dump line instead).
bit          quiet = 0;
// Strobe override: when strb_force is 1, every write beat uses strb_val as it is.
bit          strb_force = 0;
logic [7:0]  strb_val = 8'hff;
// Outstanding read requests per ID, so the tasks know the lanes of the beats that come back.
int unsigned arq_addr [0:15][0:7];
int          arq_len [0:15][0:7];
logic [2:0]  arq_size [0:15][0:7];
logic [1:0]  arq_burst [0:15][0:7];
int          arq_head [0:15], arq_tail [0:15];
initial for (int i = 0; i < 16; i++) begin arq_head[i] = 0; arq_tail[i] = 0; rdn[i] = 0; end
// READY patterns for the response channels: bit (cycle % 16) of the pattern drives the signal.
bit          rpat_on = 0, bpat_on = 0;
logic [15:0] rpat = 16'hffff, bpat = 16'hffff;
always @(posedge aclk) begin
  #1;
  if (rpat_on) rready = rpat[cycle % 16];
  if (bpat_on) bready = bpat[cycle % 16];
end

// A text waveform for the lesson's trace blocks: with watch = 1, one line per rising edge with the
// values sampled at that edge (cycle k of a trace is what edge k sees).
bit watch = 0;
int wave_edge = -1;
always @(posedge aclk) begin
  wave_edge = wave_edge + 1;
  if (watch) $display("wave e%0d: aw=%b%b w=%b%b b=%b%b ar=%b%b r=%b%b awaddr=%h wdata=%h wstrb=%b wlast=%b bid=%h bresp=%b araddr=%h rid=%h rdata=%h rresp=%b rlast=%b",
                      wave_edge, awvalid, awready, wvalid, wready, bvalid, bready, arvalid, arready, rvalid, rready,
                      awaddr, wdata, wstrb, wlast, bid, bresp, araddr, rid, rdata, rresp, rlast);
end

// Drive RREADY (ch = 0) or BREADY (ch = 1) from a 16-bit pattern; 16'hffff restores always ready.
task automatic ready_pattern(input int ch, input logic [15:0] pat);
  if (ch == 0) begin rpat = pat; rpat_on = 1; rready = pat[cycle % 16]; end
  else begin bpat = pat; bpat_on = 1; bready = pat[cycle % 16]; end
endtask

// The write address channel: offer the request and hold it until it is taken.
task automatic aw_issue(input logic [ID_W-1:0] id, input int unsigned addr, input int len, input logic [2:0] size,
                        input logic [1:0] burst, input logic lock = 0);
  awid = id; awaddr = addr; awlen = len[7:0]; awsize = size; awburst = burst; awlock = lock; awvalid = 1;
  do @(posedge aclk); while (!awready);
  #1 if (!quiet) $display("e%0d AW id=%0d addr=0x%0h len=%0d size=%0d %0s%0s", cycle, id, addr, len, size, burst_name(burst), lock ? " exclusive" : "");
  awvalid = 0; awaddr = 'x; awlen = 'x; awsize = 'x; awburst = 'x; awid = 'x; awlock = 0;
endtask

// The write data channel: the beats of one burst from wd[first..], each placed in its lanes.
task automatic w_burst(input int unsigned addr, input int len, input logic [2:0] size, input logic [1:0] burst, input int first = 0);
  logic [15:0] lanes;
  for (int n = 0; n <= len; n++) begin
    lanes = beat_lanes(addr, len, size, burst, n, BUS_BYTES);
    beat_a = beat_addr(addr, len, size, burst, n);
    beat_m = strb_force ? strb_val : beat_strb(addr, len, size, burst, n, BUS_BYTES);
    wdata = wd[first + n] << (8 * lanes[7:0]);
    wstrb = beat_m[BUS_BYTES-1:0];
    wlast = (n == len);
    wvalid = 1;
    do @(posedge aclk); while (!wready);
    #1 if (!quiet) $display("e%0d W  beat %0d data=0x%0h strb=%b last=%0d  addr 0x%0h lanes %0d-%0d", cycle, n, wdata, wstrb, wlast, beat_a, lanes[7:0], lanes[15:8]);
  end
  wvalid = 0; wdata = 'x; wstrb = 'x; wlast = 0; beat_m = 0;
endtask

// Wait for the write response of one transaction with this ID.
task automatic b_wait(input logic [ID_W-1:0] id);
  do @(posedge aclk); while (!(bvalid && bready && bid == id));
  last_bresp = bresp;                       // sampled at the edge, before the subordinate moves on
  #1 if (!quiet) $display("e%0d B  id=%0d %0s", cycle, id, resp_name(last_bresp));
endtask

// A complete write. order 0 offers the address, then the first beat one cycle later whether or
// not the address has been taken yet (a manager must never make WVALID wait for AWREADY); 1 offers
// the beats first and the address after beat 0; 2 offers the address and beat 0 in the same cycle.
// Returns after B, with the response in last_bresp.
task automatic axi_write(input logic [ID_W-1:0] id, input int unsigned addr, input int len, input logic [2:0] size,
                         input logic [1:0] burst, input int order = 0, input logic lock = 0);
  case (order)
    1: fork
         w_burst(addr, len, size, burst);
         begin @(posedge aclk); #1 aw_issue(id, addr, len, size, burst, lock); end
       join
    2: fork
         aw_issue(id, addr, len, size, burst, lock);
         w_burst(addr, len, size, burst);
       join
    default: fork
         aw_issue(id, addr, len, size, burst, lock);
         begin @(posedge aclk); #1 w_burst(addr, len, size, burst); end
       join
  endcase
  b_wait(id);
endtask

// The read address channel: offer the request and remember it for the beats that come back.
task automatic ar_issue(input logic [ID_W-1:0] id, input int unsigned addr, input int len, input logic [2:0] size,
                        input logic [1:0] burst, input logic lock = 0);
  arq_addr[id][arq_tail[id]] = addr; arq_len[id][arq_tail[id]] = len; arq_size[id][arq_tail[id]] = size;
  arq_burst[id][arq_tail[id]] = burst; arq_tail[id] = (arq_tail[id] + 1) % 8;
  arid = id; araddr = addr; arlen = len[7:0]; arsize = size; arburst = burst; arlock = lock; arvalid = 1;
  do @(posedge aclk); while (!arready);
  #1 if (!quiet) $display("e%0d AR id=%0d addr=0x%0h len=%0d size=%0d %0s%0s", cycle, id, addr, len, size, burst_name(burst), lock ? " exclusive" : "");
  arvalid = 0; araddr = 'x; arlen = 'x; arsize = 'x; arburst = 'x; arid = 'x; arlock = 0;
endtask

// Collect read beats until n transactions have ended (their RLAST). Each beat lands in rdq[rid][k]
// with only the bytes of the transfer (lane-shifted down), and rd[] holds the last transaction.
task automatic r_collect(input int n);
  int done = 0, h;
  logic [15:0] lanes;
  logic [63:0] bytes;
  logic [ID_W-1:0] id;
  logic [DATA_W-1:0] data;
  logic [1:0] resp;
  logic last;
  while (done < n) begin
    do @(posedge aclk); while (!(rvalid && rready));
    id = rid; data = rdata; resp = rresp; last = rlast;   // sampled at the edge, before the subordinate moves on
    h = arq_head[id];
    lanes = beat_lanes(arq_addr[id][h], arq_len[id][h], arq_size[id][h], arq_burst[id][h], rdn[id], BUS_BYTES);
    beat_a = beat_addr(arq_addr[id][h], arq_len[id][h], arq_size[id][h], arq_burst[id][h], rdn[id]);
    beat_m = beat_strb(arq_addr[id][h], arq_len[id][h], arq_size[id][h], arq_burst[id][h], rdn[id], BUS_BYTES);
    bytes = (data >> (8 * lanes[7:0])) & ((64'h1 << (8 * (lanes[15:8] - lanes[7:0] + 1))) - 1);
    rdq[id][rdn[id]] = bytes; rrq[id][rdn[id]] = resp;
    #1 if (!quiet) $display("e%0d R  id=%0d beat %0d data=0x%0h %0s%0s  addr 0x%0h lanes %0d-%0d", cycle, id, rdn[id], bytes, resp_name(resp),
                last ? " last" : "", beat_a, lanes[7:0], lanes[15:8]);
    rdn[id] = rdn[id] + 1;
    if (last) begin
      for (int k = 0; k < rdn[id]; k++) begin rd[k] = rdq[id][k]; rr[k] = rrq[id][k]; end
      last_beats = rdn[id]; rdn[id] = 0; arq_head[id] = (h + 1) % 8; done = done + 1;
    end
  end
  beat_m = 0;
endtask

// A complete read: AR, then every beat, into rd[] and rr[].
task automatic axi_read(input logic [ID_W-1:0] id, input int unsigned addr, input int len, input logic [2:0] size,
                        input logic [1:0] burst, input logic lock = 0);
  ar_issue(id, addr, len, size, burst, lock);
  r_collect(1);
endtask

// The table of a burst before it runs: the address, lanes and strobe of every beat.
task automatic beat_table(input int unsigned addr, input int len, input logic [2:0] size, input logic [1:0] burst);
  logic [15:0] lanes;
  logic [63:0] s;
  int unsigned a;
  $display("burst at 0x%0h: %0d beat%0s of %0d byte%0s, %0s, bus %0d bytes", addr, len + 1, len ? "s" : "", 1 << size, size ? "s" : "",
           burst_name(burst), BUS_BYTES);
  $display("  beat  address  lanes  strobe");
  for (int n = 0; n <= len; n++) begin
    lanes = beat_lanes(addr, len, size, burst, n, BUS_BYTES);
    s = beat_strb(addr, len, size, burst, n, BUS_BYTES);
    a = beat_addr(addr, len, size, burst, n);
    $display("  %4d  0x%05h  %0d-%0d    %b", n, a[19:0], lanes[7:0], lanes[15:8], s[BUS_BYTES-1:0]);
  end
  if (crosses_4k(addr, len, size, burst)) $display("  this burst crosses a 4 KB boundary");
endtask

// One byte of the memory that owns an address (the fabric's second memory above 0x8000).
function automatic logic [7:0] mem_byte(input int unsigned a);
`ifdef AXI_MEM1
  if (a >= 32'h8000) return `AXI_MEM1.mem[a];
`endif
  return `AXI_MEM.mem[a];
endfunction
task automatic set_byte(input int unsigned a, input logic [7:0] v);
`ifdef AXI_MEM1
  if (a >= 32'h8000) `AXI_MEM1.mem[a] = v;
  else `AXI_MEM.mem[a] = v;
`else
  `AXI_MEM.mem[a] = v;
`endif
endtask

// The memory, n bytes from addr, one bus word per group.
task automatic dump(input int unsigned addr, input int n);
  string line;
  int unsigned a = (addr / 16) * 16;
  while (a < addr + n) begin
    line = $sformatf("0x%05h ", a[19:0]);
    for (int i = 0; i < 16; i++) begin
      if (i % BUS_BYTES == 0) line = {line, " "};
      line = {line, $sformatf(" %02h", mem_byte(a + i))};
    end
    $display("%s", line);
    a = a + 16;
  end
endtask

// Fill n bytes from addr with first, first+1, ... so untouched bytes stay recognisable.
task automatic mem_fill(input int unsigned addr, input int n, input logic [7:0] first = 8'h00);
  for (int i = 0; i < n; i++) set_byte(addr + i, first + i[7:0]);
endtask

// Drive nothing for n cycles.
task automatic idle(input int n);
  repeat (n) @(posedge aclk);
  #1;
endtask

Check yourself

Predict the outputThe stimulus reads the ID register at 0xc by hand on a bench without the checker, so only its own line prints. What is the line?

`timescale 1ns/1ps
// axi_lite_regs: four 32-bit registers on an AXI4-Lite interface, with ID reflection so a full AXI
// manager can talk to it directly (read-only in this lesson).
//   0x0 CTRL   read/write        0x8 STATUS  read-only (a write gets SLVERR)
//   0x4 DATA   read/write        0xc ID      read-only, 0x4c495445 ("LITE")
// Every transaction is one transfer of the full bus width; the strobes select the bytes of a write.
// An offset at or above 0x10 is outside the block: DECERR.
module axi_lite_regs #(parameter int ID_W = 4) (
  input  logic            aclk,
  input  logic            aresetn,
  input  logic [ID_W-1:0] awid,
  input  logic [31:0]     awaddr,
  input  logic [2:0]      awprot,
  input  logic            awvalid,
  output logic            awready,
  input  logic [31:0]     wdata,
  input  logic [3:0]      wstrb,
  input  logic            wvalid,
  output logic            wready,
  output logic [ID_W-1:0] bid,
  output logic [1:0]      bresp,
  output logic            bvalid,
  input  logic            bready,
  input  logic [ID_W-1:0] arid,
  input  logic [31:0]     araddr,
  input  logic [2:0]      arprot,
  input  logic            arvalid,
  output logic            arready,
  output logic [ID_W-1:0] rid,
  output logic [31:0]     rdata,
  output logic [1:0]      rresp,
  output logic            rlast,
  output logic            rvalid,
  input  logic            rready
);
  import axi_pkg::*;
  logic [7:0] mem [0:15];                   // the registers' bytes, lane 0 at the lowest address
  initial begin
    for (int i = 0; i < 16; i++) mem[i] = 8'h00;
    mem[8] = 8'h01;                                                   // STATUS: bit 0 = ready
    mem[12] = 8'h45; mem[13] = 8'h54; mem[14] = 8'h49; mem[15] = 8'h4c; // ID = 0x4c495445
    awready = 0; wready = 0; arready = 0; bvalid = 0; rvalid = 0; bid = 0; bresp = 0; rid = 0; rresp = 0; rdata = 0;
  end
  assign rlast = 1'b1;                      // AXI4-Lite has no RLAST: every transfer is the last
  logic aw_v = 0, w_v = 0;
  logic [31:0]     aw_addr, w_data;
  logic [ID_W-1:0] aw_id;
  logic [3:0]      w_strb;
  always @(posedge aclk) begin
    if (!aresetn) begin
      aw_v = 0; w_v = 0; awready <= 0; wready <= 0; arready <= 0; bvalid <= 0; rvalid <= 0;
    end else begin
      if (awvalid && awready) begin aw_v = 1; aw_addr = awaddr; aw_id = awid; end
      if (wvalid && wready) begin w_v = 1; w_data = wdata; w_strb = wstrb; end
      if (bvalid && bready) bvalid <= 0;
      if (aw_v && w_v && !(bvalid && !bready)) begin      // address and data both here, B channel free
        if (aw_addr[31:4] != 0) bresp <= DECERR;
        else if (aw_addr[3:2] >= 2) bresp <= SLVERR;      // STATUS and ID are read-only
        else begin
          bresp <= OKAY;
          for (int l = 0; l < 4; l++) if (w_strb[l]) mem[{aw_addr[3:2], l[1:0]}] = w_data[8*l +: 8];
        end
        bid <= aw_id; bvalid <= 1; aw_v = 0; w_v = 0;
      end
      if (rvalid && rready) rvalid <= 0;
      if (arvalid && arready) begin
        rid <= arid; rvalid <= 1;
        if (araddr[31:4] != 0) begin rresp <= DECERR; rdata <= 32'h0; end
        else begin
          rresp <= OKAY;
          rdata <= {mem[{araddr[3:2], 2'b11}], mem[{araddr[3:2], 2'b10}], mem[{araddr[3:2], 2'b01}], mem[{araddr[3:2], 2'b00}]};
        end
      end
      awready <= !aw_v;
      wready  <= !w_v;
      arready <= !rvalid || rready;
    end
  end
endmodule

module tb;
  import axi_pkg::*;
  localparam int DATA_W = 32, ID_W = 4, BUS_BYTES = DATA_W / 8;
  logic aclk = 0, aresetn = 0;
  always #5 aclk = ~aclk;                 // rising edges at 5, 15, 25, ...
  logic [ID_W-1:0]   awid = 0, bid, arid = 0, rid;
  logic [31:0]       awaddr = 0, araddr = 0;
  logic [7:0]        awlen = 0, arlen = 0;
  logic [2:0]        awsize = 0, arsize = 0;
  logic [1:0]        awburst = 0, arburst = 0, bresp, rresp;
  logic              awlock = 0, arlock = 0;
  logic [3:0]        awcache = 0, arcache = 0;
  logic [2:0]        awprot = 0, arprot = 0;
  logic              awvalid = 0, awready, wvalid = 0, wready, wlast = 0, bvalid, bready = 1;
  logic              arvalid = 0, arready, rvalid, rlast, rready = 1;
  logic [DATA_W-1:0] wdata = 0, rdata;
  logic [DATA_W/8-1:0] wstrb = 0;
  axi_lite_regs #(.ID_W(ID_W)) regs (.aclk(aclk), .aresetn(aresetn),
    .awid(awid), .awaddr(awaddr), .awprot(awprot), .awvalid(awvalid), .awready(awready),
    .wdata(wdata), .wstrb(wstrb), .wvalid(wvalid), .wready(wready),
    .bid(bid), .bresp(bresp), .bvalid(bvalid), .bready(bready),
    .arid(arid), .araddr(araddr), .arprot(arprot), .arvalid(arvalid), .arready(arready),
    .rid(rid), .rdata(rdata), .rresp(rresp), .rlast(rlast), .rvalid(rvalid), .rready(rready));
  `define AXI_MEM regs
  
  `include "axi_tasks.svh"
  initial begin
    repeat (2) @(posedge aclk); #1 aresetn = 1;   // reset released after edge 1
    @(posedge aclk); #1;                          // the first request may start after edge 2
    araddr = 32'hc; arid = 0; arvalid = 1;
    do @(posedge aclk); while (!arready);
    #1 arvalid = 0;
    do @(posedge aclk); while (!(rvalid && rready));
    $display("ID register = 0x%08h %0s", rdata, resp_name(rresp));
    #1;
    repeat (3) @(posedge aclk);
    $finish;
  end
endmodule

Read included file: axi_pkg.sv

`timescale 1ns/1ns
// axi_pkg.sv: the arithmetic of a burst (read-only).
// Every transfer n of a burst has an address and a set of byte lanes, computed from the start
// address, the burst length, the transfer size and the burst type exactly as the AXI specification
// defines them. The memory, the manager tasks and the checker all use these functions, so they
// never disagree about where a byte lands.
package axi_pkg;
  localparam logic [1:0] FIXED = 2'b00, INCR = 2'b01, WRAP = 2'b10;
  localparam logic [1:0] OKAY = 2'b00, EXOKAY = 2'b01, SLVERR = 2'b10, DECERR = 2'b11;

  function automatic string burst_name(input logic [1:0] b);
    case (b) FIXED: return "FIXED"; INCR: return "INCR"; WRAP: return "WRAP"; default: return "RESERVED"; endcase
  endfunction
  function automatic string resp_name(input logic [1:0] r);
    case (r) OKAY: return "OKAY"; EXOKAY: return "EXOKAY"; SLVERR: return "SLVERR"; default: return "DECERR"; endcase
  endfunction

  // Bytes in one transfer: 1, 2, 4, ... 128.
  function automatic int bytes_of(input logic [2:0] size);
    return 1 << size;
  endfunction

  // The address of transfer n (n counts from 0).
  //   transfer 0 uses the start address as given, aligned or not;
  //   later transfers use the start address aligned down to the transfer size, plus n transfers;
  //   a WRAP burst returns to its wrap boundary (the start aligned down to the whole burst) when
  //   it reaches the end of that window; a FIXED burst repeats the start address.
  function automatic int unsigned beat_addr(input int unsigned start, input int len, input logic [2:0] size,
                                            input logic [1:0] burst, input int n);
    int unsigned nb = 1 << size;
    int unsigned aligned = (start / nb) * nb;
    int unsigned window = nb * (len + 1);
    int unsigned boundary = (start / window) * window;
    int unsigned a;
    if (burst == FIXED || n == 0) return start;
    a = aligned + n * nb;
    if (burst == WRAP && a >= boundary + window) a = a - window;
    return a;
  endfunction

  // The byte lanes transfer n uses on a bus of bus_bytes bytes, packed as {upper, lower}.
  // Transfer 0 of an unaligned burst (and every transfer of a FIXED burst) uses only the lanes from
  // its address up to the end of its aligned transfer; every other transfer uses all the lanes of
  // its size.
  function automatic logic [15:0] beat_lanes(input int unsigned start, input int len, input logic [2:0] size,
                                             input logic [1:0] burst, input int n, input int bus_bytes);
    int unsigned nb = 1 << size;
    int unsigned a = beat_addr(start, len, size, burst, n);
    int unsigned aligned = (a / nb) * nb;
    int unsigned word = (a / bus_bytes) * bus_bytes;
    int lower = a - word;
    int upper = (n == 0 || burst == FIXED) ? (aligned + nb - 1 - word) : (lower + nb - 1);
    return {upper[7:0], lower[7:0]};
  endfunction

  // The strobe of transfer n: a 1 for every lane it uses (bit l is lane l).
  function automatic logic [63:0] beat_strb(input int unsigned start, input int len, input logic [2:0] size,
                                            input logic [1:0] burst, input int n, input int bus_bytes);
    logic [15:0] lanes = beat_lanes(start, len, size, burst, n, bus_bytes);
    logic [63:0] s = 0;
    for (int l = lanes[7:0]; l <= lanes[15:8]; l++) s[l] = 1'b1;
    return s;
  endfunction

  // True when the burst crosses a 4 KB boundary (only an INCR burst can).
  function automatic bit crosses_4k(input int unsigned start, input int len, input logic [2:0] size, input logic [1:0] burst);
    if (burst != INCR) return 0;
    return (beat_addr(start, len, size, burst, 0) / 4096) != ((beat_addr(start, len, size, burst, len) + (1 << size) - 1) / 4096);
  endfunction
endpackage

Read included file: axi_tasks.svh

// axi_tasks.svh: the manager side of the bench, as tasks for the stimulus (read-only).
// Data for a write burst goes in wd[0], wd[1], ... (one entry per beat, the lowest byte at the
// lowest address); the data of a read comes back in rd[0], rd[1], ... with its responses in rr[].
// Every task prints the beat log: one line per handshake, with the edge where it happened.
// `cycle` counts rising edges from 0.
int cycle = -1;
always @(posedge aclk) cycle = cycle + 1;

logic [63:0] wd [0:255];
logic [63:0] rd [0:255];
logic [1:0]  rr [0:255];
logic [63:0] rdq [0:15][0:255];     // read data per ID, for reads collected out of order
logic [1:0]  rrq [0:15][0:255];
int          rdn [0:15];            // beats received per ID
logic [1:0]  last_bresp = 0;
int          last_beats = 0;
// What the task is driving right now, for the waveform scenes: the address and lanes of the beat.
int unsigned beat_a = 0;
logic [7:0]  beat_m = 0;
// quiet = 1 silences the beat log (a predict item can then ask for a dump line instead).
bit          quiet = 0;
// Strobe override: when strb_force is 1, every write beat uses strb_val as it is.
bit          strb_force = 0;
logic [7:0]  strb_val = 8'hff;
// Outstanding read requests per ID, so the tasks know the lanes of the beats that come back.
int unsigned arq_addr [0:15][0:7];
int          arq_len [0:15][0:7];
logic [2:0]  arq_size [0:15][0:7];
logic [1:0]  arq_burst [0:15][0:7];
int          arq_head [0:15], arq_tail [0:15];
initial for (int i = 0; i < 16; i++) begin arq_head[i] = 0; arq_tail[i] = 0; rdn[i] = 0; end
// READY patterns for the response channels: bit (cycle % 16) of the pattern drives the signal.
bit          rpat_on = 0, bpat_on = 0;
logic [15:0] rpat = 16'hffff, bpat = 16'hffff;
always @(posedge aclk) begin
  #1;
  if (rpat_on) rready = rpat[cycle % 16];
  if (bpat_on) bready = bpat[cycle % 16];
end

// A text waveform for the lesson's trace blocks: with watch = 1, one line per rising edge with the
// values sampled at that edge (cycle k of a trace is what edge k sees).
bit watch = 0;
int wave_edge = -1;
always @(posedge aclk) begin
  wave_edge = wave_edge + 1;
  if (watch) $display("wave e%0d: aw=%b%b w=%b%b b=%b%b ar=%b%b r=%b%b awaddr=%h wdata=%h wstrb=%b wlast=%b bid=%h bresp=%b araddr=%h rid=%h rdata=%h rresp=%b rlast=%b",
                      wave_edge, awvalid, awready, wvalid, wready, bvalid, bready, arvalid, arready, rvalid, rready,
                      awaddr, wdata, wstrb, wlast, bid, bresp, araddr, rid, rdata, rresp, rlast);
end

// Drive RREADY (ch = 0) or BREADY (ch = 1) from a 16-bit pattern; 16'hffff restores always ready.
task automatic ready_pattern(input int ch, input logic [15:0] pat);
  if (ch == 0) begin rpat = pat; rpat_on = 1; rready = pat[cycle % 16]; end
  else begin bpat = pat; bpat_on = 1; bready = pat[cycle % 16]; end
endtask

// The write address channel: offer the request and hold it until it is taken.
task automatic aw_issue(input logic [ID_W-1:0] id, input int unsigned addr, input int len, input logic [2:0] size,
                        input logic [1:0] burst, input logic lock = 0);
  awid = id; awaddr = addr; awlen = len[7:0]; awsize = size; awburst = burst; awlock = lock; awvalid = 1;
  do @(posedge aclk); while (!awready);
  #1 if (!quiet) $display("e%0d AW id=%0d addr=0x%0h len=%0d size=%0d %0s%0s", cycle, id, addr, len, size, burst_name(burst), lock ? " exclusive" : "");
  awvalid = 0; awaddr = 'x; awlen = 'x; awsize = 'x; awburst = 'x; awid = 'x; awlock = 0;
endtask

// The write data channel: the beats of one burst from wd[first..], each placed in its lanes.
task automatic w_burst(input int unsigned addr, input int len, input logic [2:0] size, input logic [1:0] burst, input int first = 0);
  logic [15:0] lanes;
  for (int n = 0; n <= len; n++) begin
    lanes = beat_lanes(addr, len, size, burst, n, BUS_BYTES);
    beat_a = beat_addr(addr, len, size, burst, n);
    beat_m = strb_force ? strb_val : beat_strb(addr, len, size, burst, n, BUS_BYTES);
    wdata = wd[first + n] << (8 * lanes[7:0]);
    wstrb = beat_m[BUS_BYTES-1:0];
    wlast = (n == len);
    wvalid = 1;
    do @(posedge aclk); while (!wready);
    #1 if (!quiet) $display("e%0d W  beat %0d data=0x%0h strb=%b last=%0d  addr 0x%0h lanes %0d-%0d", cycle, n, wdata, wstrb, wlast, beat_a, lanes[7:0], lanes[15:8]);
  end
  wvalid = 0; wdata = 'x; wstrb = 'x; wlast = 0; beat_m = 0;
endtask

// Wait for the write response of one transaction with this ID.
task automatic b_wait(input logic [ID_W-1:0] id);
  do @(posedge aclk); while (!(bvalid && bready && bid == id));
  last_bresp = bresp;                       // sampled at the edge, before the subordinate moves on
  #1 if (!quiet) $display("e%0d B  id=%0d %0s", cycle, id, resp_name(last_bresp));
endtask

// A complete write. order 0 offers the address, then the first beat one cycle later whether or
// not the address has been taken yet (a manager must never make WVALID wait for AWREADY); 1 offers
// the beats first and the address after beat 0; 2 offers the address and beat 0 in the same cycle.
// Returns after B, with the response in last_bresp.
task automatic axi_write(input logic [ID_W-1:0] id, input int unsigned addr, input int len, input logic [2:0] size,
                         input logic [1:0] burst, input int order = 0, input logic lock = 0);
  case (order)
    1: fork
         w_burst(addr, len, size, burst);
         begin @(posedge aclk); #1 aw_issue(id, addr, len, size, burst, lock); end
       join
    2: fork
         aw_issue(id, addr, len, size, burst, lock);
         w_burst(addr, len, size, burst);
       join
    default: fork
         aw_issue(id, addr, len, size, burst, lock);
         begin @(posedge aclk); #1 w_burst(addr, len, size, burst); end
       join
  endcase
  b_wait(id);
endtask

// The read address channel: offer the request and remember it for the beats that come back.
task automatic ar_issue(input logic [ID_W-1:0] id, input int unsigned addr, input int len, input logic [2:0] size,
                        input logic [1:0] burst, input logic lock = 0);
  arq_addr[id][arq_tail[id]] = addr; arq_len[id][arq_tail[id]] = len; arq_size[id][arq_tail[id]] = size;
  arq_burst[id][arq_tail[id]] = burst; arq_tail[id] = (arq_tail[id] + 1) % 8;
  arid = id; araddr = addr; arlen = len[7:0]; arsize = size; arburst = burst; arlock = lock; arvalid = 1;
  do @(posedge aclk); while (!arready);
  #1 if (!quiet) $display("e%0d AR id=%0d addr=0x%0h len=%0d size=%0d %0s%0s", cycle, id, addr, len, size, burst_name(burst), lock ? " exclusive" : "");
  arvalid = 0; araddr = 'x; arlen = 'x; arsize = 'x; arburst = 'x; arid = 'x; arlock = 0;
endtask

// Collect read beats until n transactions have ended (their RLAST). Each beat lands in rdq[rid][k]
// with only the bytes of the transfer (lane-shifted down), and rd[] holds the last transaction.
task automatic r_collect(input int n);
  int done = 0, h;
  logic [15:0] lanes;
  logic [63:0] bytes;
  logic [ID_W-1:0] id;
  logic [DATA_W-1:0] data;
  logic [1:0] resp;
  logic last;
  while (done < n) begin
    do @(posedge aclk); while (!(rvalid && rready));
    id = rid; data = rdata; resp = rresp; last = rlast;   // sampled at the edge, before the subordinate moves on
    h = arq_head[id];
    lanes = beat_lanes(arq_addr[id][h], arq_len[id][h], arq_size[id][h], arq_burst[id][h], rdn[id], BUS_BYTES);
    beat_a = beat_addr(arq_addr[id][h], arq_len[id][h], arq_size[id][h], arq_burst[id][h], rdn[id]);
    beat_m = beat_strb(arq_addr[id][h], arq_len[id][h], arq_size[id][h], arq_burst[id][h], rdn[id], BUS_BYTES);
    bytes = (data >> (8 * lanes[7:0])) & ((64'h1 << (8 * (lanes[15:8] - lanes[7:0] + 1))) - 1);
    rdq[id][rdn[id]] = bytes; rrq[id][rdn[id]] = resp;
    #1 if (!quiet) $display("e%0d R  id=%0d beat %0d data=0x%0h %0s%0s  addr 0x%0h lanes %0d-%0d", cycle, id, rdn[id], bytes, resp_name(resp),
                last ? " last" : "", beat_a, lanes[7:0], lanes[15:8]);
    rdn[id] = rdn[id] + 1;
    if (last) begin
      for (int k = 0; k < rdn[id]; k++) begin rd[k] = rdq[id][k]; rr[k] = rrq[id][k]; end
      last_beats = rdn[id]; rdn[id] = 0; arq_head[id] = (h + 1) % 8; done = done + 1;
    end
  end
  beat_m = 0;
endtask

// A complete read: AR, then every beat, into rd[] and rr[].
task automatic axi_read(input logic [ID_W-1:0] id, input int unsigned addr, input int len, input logic [2:0] size,
                        input logic [1:0] burst, input logic lock = 0);
  ar_issue(id, addr, len, size, burst, lock);
  r_collect(1);
endtask

// The table of a burst before it runs: the address, lanes and strobe of every beat.
task automatic beat_table(input int unsigned addr, input int len, input logic [2:0] size, input logic [1:0] burst);
  logic [15:0] lanes;
  logic [63:0] s;
  int unsigned a;
  $display("burst at 0x%0h: %0d beat%0s of %0d byte%0s, %0s, bus %0d bytes", addr, len + 1, len ? "s" : "", 1 << size, size ? "s" : "",
           burst_name(burst), BUS_BYTES);
  $display("  beat  address  lanes  strobe");
  for (int n = 0; n <= len; n++) begin
    lanes = beat_lanes(addr, len, size, burst, n, BUS_BYTES);
    s = beat_strb(addr, len, size, burst, n, BUS_BYTES);
    a = beat_addr(addr, len, size, burst, n);
    $display("  %4d  0x%05h  %0d-%0d    %b", n, a[19:0], lanes[7:0], lanes[15:8], s[BUS_BYTES-1:0]);
  end
  if (crosses_4k(addr, len, size, burst)) $display("  this burst crosses a 4 KB boundary");
endtask

// One byte of the memory that owns an address (the fabric's second memory above 0x8000).
function automatic logic [7:0] mem_byte(input int unsigned a);
`ifdef AXI_MEM1
  if (a >= 32'h8000) return `AXI_MEM1.mem[a];
`endif
  return `AXI_MEM.mem[a];
endfunction
task automatic set_byte(input int unsigned a, input logic [7:0] v);
`ifdef AXI_MEM1
  if (a >= 32'h8000) `AXI_MEM1.mem[a] = v;
  else `AXI_MEM.mem[a] = v;
`else
  `AXI_MEM.mem[a] = v;
`endif
endtask

// The memory, n bytes from addr, one bus word per group.
task automatic dump(input int unsigned addr, input int n);
  string line;
  int unsigned a = (addr / 16) * 16;
  while (a < addr + n) begin
    line = $sformatf("0x%05h ", a[19:0]);
    for (int i = 0; i < 16; i++) begin
      if (i % BUS_BYTES == 0) line = {line, " "};
      line = {line, $sformatf(" %02h", mem_byte(a + i))};
    end
    $display("%s", line);
    a = a + 16;
  end
endtask

// Fill n bytes from addr with first, first+1, ... so untouched bytes stay recognisable.
task automatic mem_fill(input int unsigned addr, input int n, input logic [7:0] first = 8'h00);
  for (int i = 0; i < n; i++) set_byte(addr + i, first + i[7:0]);
endtask

// Drive nothing for n cycles.
task automatic idle(input int n);
  repeat (n) @(posedge aclk);
  #1;
endtask

Spot the bugEach option is one transaction into the register block, issued with the full-AXI task library. Which one makes the checker name a broken rule, so that the harness prints FAIL?

wd[0] = 32'h1234; axi_write(0, 32'h4, 0, 1, INCR);

axi_read(0, 32'h8, 0, 2, INCR);

wd[0] = 32'h5; axi_write(0, 32'h4, 0, 2, INCR);

axi_read(0, 32'h0, 1, 2, INCR);

Read included file: axi_pkg.sv

`timescale 1ns/1ns
// axi_pkg.sv: the arithmetic of a burst (read-only).
// Every transfer n of a burst has an address and a set of byte lanes, computed from the start
// address, the burst length, the transfer size and the burst type exactly as the AXI specification
// defines them. The memory, the manager tasks and the checker all use these functions, so they
// never disagree about where a byte lands.
package axi_pkg;
  localparam logic [1:0] FIXED = 2'b00, INCR = 2'b01, WRAP = 2'b10;
  localparam logic [1:0] OKAY = 2'b00, EXOKAY = 2'b01, SLVERR = 2'b10, DECERR = 2'b11;

  function automatic string burst_name(input logic [1:0] b);
    case (b) FIXED: return "FIXED"; INCR: return "INCR"; WRAP: return "WRAP"; default: return "RESERVED"; endcase
  endfunction
  function automatic string resp_name(input logic [1:0] r);
    case (r) OKAY: return "OKAY"; EXOKAY: return "EXOKAY"; SLVERR: return "SLVERR"; default: return "DECERR"; endcase
  endfunction

  // Bytes in one transfer: 1, 2, 4, ... 128.
  function automatic int bytes_of(input logic [2:0] size);
    return 1 << size;
  endfunction

  // The address of transfer n (n counts from 0).
  //   transfer 0 uses the start address as given, aligned or not;
  //   later transfers use the start address aligned down to the transfer size, plus n transfers;
  //   a WRAP burst returns to its wrap boundary (the start aligned down to the whole burst) when
  //   it reaches the end of that window; a FIXED burst repeats the start address.
  function automatic int unsigned beat_addr(input int unsigned start, input int len, input logic [2:0] size,
                                            input logic [1:0] burst, input int n);
    int unsigned nb = 1 << size;
    int unsigned aligned = (start / nb) * nb;
    int unsigned window = nb * (len + 1);
    int unsigned boundary = (start / window) * window;
    int unsigned a;
    if (burst == FIXED || n == 0) return start;
    a = aligned + n * nb;
    if (burst == WRAP && a >= boundary + window) a = a - window;
    return a;
  endfunction

  // The byte lanes transfer n uses on a bus of bus_bytes bytes, packed as {upper, lower}.
  // Transfer 0 of an unaligned burst (and every transfer of a FIXED burst) uses only the lanes from
  // its address up to the end of its aligned transfer; every other transfer uses all the lanes of
  // its size.
  function automatic logic [15:0] beat_lanes(input int unsigned start, input int len, input logic [2:0] size,
                                             input logic [1:0] burst, input int n, input int bus_bytes);
    int unsigned nb = 1 << size;
    int unsigned a = beat_addr(start, len, size, burst, n);
    int unsigned aligned = (a / nb) * nb;
    int unsigned word = (a / bus_bytes) * bus_bytes;
    int lower = a - word;
    int upper = (n == 0 || burst == FIXED) ? (aligned + nb - 1 - word) : (lower + nb - 1);
    return {upper[7:0], lower[7:0]};
  endfunction

  // The strobe of transfer n: a 1 for every lane it uses (bit l is lane l).
  function automatic logic [63:0] beat_strb(input int unsigned start, input int len, input logic [2:0] size,
                                            input logic [1:0] burst, input int n, input int bus_bytes);
    logic [15:0] lanes = beat_lanes(start, len, size, burst, n, bus_bytes);
    logic [63:0] s = 0;
    for (int l = lanes[7:0]; l <= lanes[15:8]; l++) s[l] = 1'b1;
    return s;
  endfunction

  // True when the burst crosses a 4 KB boundary (only an INCR burst can).
  function automatic bit crosses_4k(input int unsigned start, input int len, input logic [2:0] size, input logic [1:0] burst);
    if (burst != INCR) return 0;
    return (beat_addr(start, len, size, burst, 0) / 4096) != ((beat_addr(start, len, size, burst, len) + (1 << size) - 1) / 4096);
  endfunction
endpackage

Read included file: axi_mem.sv

`timescale 1ns/1ns
// axi_mem.sv: an AXI4 subordinate with a byte-addressed memory behind it (read-only in this lesson).
// It accepts requests on AW and AR, write beats on W (before or after their AW), writes the bytes a
// burst addresses using the strobes, and answers on B and R after a latency. The switches below are
// plain variables: the stimulus sets them by name (mem.reorder = 1;) before it starts.
//   rd_latency, wr_latency   cycles from a request (or its last write beat) to its first response
//   slow_latency, slow_above addresses at or above slow_above answer after slow_latency instead
//   err_above                addresses at or above err_above get SLVERR (and are not written)
//   reorder                  answer transactions with DIFFERENT IDs as soon as each is ready;
//                            transactions with the same ID still answer in order
//   interleave               interleave the read data beats of ready transactions with different IDs
//   excl_on                  support exclusive access (one monitor per ID), else answer OKAY
//   posted                   apply a write to the memory only when its response is sent, so a read
//                            that arrives between the last beat and B still sees the old bytes
//   trace                    print every byte the memory writes
// Broken twins, each off by default: early_b (B before the last write beat and before AW),
// ignore_strobes (write every lane of the bus word), drop_hold (RDATA changes while RVALID waits
// for RREADY), reorder_same_id (a later transaction with the same ID may answer first),
// wrap_bug (a WRAP burst addressed like INCR).
module axi_mem #(parameter int DATA_W = 32, parameter int ID_W = 4, parameter int DEPTH = 65536) (
  input  logic              aclk,
  input  logic              aresetn,
  input  logic [ID_W-1:0]   awid,
  input  logic [31:0]       awaddr,
  input  logic [7:0]        awlen,
  input  logic [2:0]        awsize,
  input  logic [1:0]        awburst,
  input  logic              awlock,
  input  logic [3:0]        awcache,
  input  logic [2:0]        awprot,
  input  logic              awvalid,
  output logic              awready,
  input  logic [DATA_W-1:0] wdata,
  input  logic [DATA_W/8-1:0] wstrb,
  input  logic              wlast,
  input  logic              wvalid,
  output logic              wready,
  output logic [ID_W-1:0]   bid,
  output logic [1:0]        bresp,
  output logic              bvalid,
  input  logic              bready,
  input  logic [ID_W-1:0]   arid,
  input  logic [31:0]       araddr,
  input  logic [7:0]        arlen,
  input  logic [2:0]        arsize,
  input  logic [1:0]        arburst,
  input  logic              arlock,
  input  logic [3:0]        arcache,
  input  logic [2:0]        arprot,
  input  logic              arvalid,
  output logic              arready,
  output logic [ID_W-1:0]   rid,
  output logic [DATA_W-1:0] rdata,
  output logic [1:0]        rresp,
  output logic              rlast,
  output logic              rvalid,
  input  logic              rready
);
  import axi_pkg::*;
  localparam int BUS = DATA_W / 8;
  localparam int N = 16;                      // transactions in flight per direction

  // ---- switches ----
  int rd_latency = 2, wr_latency = 2, slow_latency = 8;
  int unsigned slow_above = 32'hffff_ffff, err_above = 32'hffff_ffff;
  bit reorder = 0, interleave = 0, excl_on = 0, posted = 0, trace = 0;
  bit early_b = 0, ignore_strobes = 0, drop_hold = 0, reorder_same_id = 0, wrap_bug = 0;

  // ---- the memory ----
  logic [7:0] mem [0:DEPTH-1];
  initial for (int i = 0; i < DEPTH; i++) mem[i] = 8'h00;

  int cycle = -1;
  int seq = 0;                                // every request gets a sequence number: issue order

  // ---- write side: accepted AW requests (a ring) and write beats (a ring) ----
  logic [ID_W-1:0] aw_id [0:N-1];
  int unsigned     aw_addr [0:N-1];
  int              aw_len [0:N-1];
  logic [2:0]      aw_size [0:N-1];
  logic [1:0]      aw_burst [0:N-1];
  logic            aw_lock [0:N-1];
  int aw_head = 0, aw_tail = 0, aw_count = 0;
  localparam int WQ = 1024;
  logic [DATA_W-1:0] w_data [0:WQ-1];
  logic [BUS-1:0]    w_strb [0:WQ-1];
  logic              w_last [0:WQ-1];
  int w_head = 0, w_tail = 0, w_count = 0, w_bursts = 0;   // w_bursts: complete bursts in the ring

  // ---- write responses waiting for their latency ----
  logic            b_use [0:N-1];
  logic [ID_W-1:0] b_id [0:N-1];
  logic [1:0]      b_rsp [0:N-1];
  int              b_at [0:N-1], b_seq [0:N-1];
  logic            b_driving = 0;
  logic            early_done = 0;            // the early_b twin answers once per burst
  // posted writes: the beats of a write kept until its response goes out
  logic [DATA_W-1:0] p_data [0:N-1][0:255];
  logic [BUS-1:0]    p_strb [0:N-1][0:255];
  int unsigned       p_addr [0:N-1];
  int                p_len [0:N-1];
  logic [2:0]        p_size [0:N-1];
  logic [1:0]        p_burst [0:N-1];
  logic              p_pending [0:N-1];

  // ---- read side: accepted AR requests with their progress ----
  logic            r_use [0:N-1];
  logic [ID_W-1:0] r_id [0:N-1];
  int unsigned     r_addr [0:N-1];
  int              r_len [0:N-1];
  logic [2:0]      r_size [0:N-1];
  logic [1:0]      r_burst [0:N-1];
  logic            r_lock [0:N-1];
  int              r_at [0:N-1], r_seq [0:N-1], r_beat [0:N-1], r_served [0:N-1];
  int              r_cur = -1;                // the transaction whose beat is on the wires
  logic            r_driving = 0;

  // ---- exclusive monitors, one per ID ----
  logic        mon_use [0:(1<<ID_W)-1];
  int unsigned mon_addr [0:(1<<ID_W)-1];
  int unsigned mon_bytes [0:(1<<ID_W)-1];

  initial begin
    for (int i = 0; i < N; i++) begin b_use[i] = 0; r_use[i] = 0; p_pending[i] = 0; end
    for (int i = 0; i < (1 << ID_W); i++) mon_use[i] = 0;
    awready = 0; wready = 0; arready = 0; bvalid = 0; rvalid = 0; bid = 0; bresp = 0; rid = 0; rresp = 0; rlast = 0; rdata = 0;
  end

  function automatic int latency_of(input int unsigned a, input int base);
    return (a >= slow_above) ? slow_latency : base;
  endfunction
  function automatic logic [1:0] burst_used(input logic [1:0] b);
    return (wrap_bug && b == WRAP) ? INCR : b;
  endfunction

  // ---- selection policies ----
  // The oldest of all pending entries, or the oldest of its ID: the in-order rule of the protocol.
  function automatic bit b_oldest(input int i, input bit same_id_only);
    for (int j = 0; j < N; j++)
      if (b_use[j] && j != i && b_seq[j] < b_seq[i] && (!same_id_only || b_id[j] == b_id[i])) return 0;
    return 1;
  endfunction
  function automatic bit r_oldest(input int i, input bit same_id_only);
    for (int j = 0; j < N; j++)
      if (r_use[j] && j != i && r_seq[j] < r_seq[i] && (!same_id_only || r_id[j] == r_id[i])) return 0;
    return 1;
  endfunction
  function automatic bit b_eligible(input int i);
    if (!b_use[i] || b_at[i] > cycle) return 0;
    if (!reorder) return b_oldest(i, 0);
    return reorder_same_id ? 1 : b_oldest(i, 1);
  endfunction
  function automatic bit r_eligible(input int i);
    if (!r_use[i] || r_at[i] > cycle) return 0;
    if (!reorder) return r_oldest(i, 0);
    return reorder_same_id ? 1 : r_oldest(i, 1);
  endfunction
  function automatic int free_b();
    for (int i = 0; i < N; i++) if (!b_use[i]) return i;
    return -1;
  endfunction
  function automatic int free_r();
    for (int i = 0; i < N; i++) if (!r_use[i]) return i;
    return -1;
  endfunction
  function automatic int pick_b();
    int best = -1;
    for (int i = 0; i < N; i++) if (b_eligible(i) && (best < 0 || b_seq[i] < b_seq[best])) best = i;
    return best;
  endfunction
  function automatic int pick_r();
    int best = -1;
    for (int i = 0; i < N; i++) if (r_eligible(i)) begin
      if (best < 0) best = i;
      else if (interleave ? (r_served[i] < r_served[best]) : (r_seq[i] < r_seq[best])) best = i;
    end
    return best;
  endfunction

  // ---- the bytes of one read beat, as the bus word that holds them ----
  function automatic logic [DATA_W-1:0] read_word(input int unsigned a);
    logic [DATA_W-1:0] d = 0;
    int unsigned word = (a / BUS) * BUS;
    for (int l = 0; l < BUS; l++) d[8*l +: 8] = (word + l < DEPTH) ? mem[word + l] : 8'h00;
    return d;
  endfunction

  // ---- the write of one complete burst into the memory ----
  task automatic write_burst(input int e);
    logic [1:0]  rsp = OKAY;
    logic        do_write = 1, ended = 0;
    int unsigned a, word;
    logic [15:0] lanes;
    int          n = 0, slot;
    int unsigned total = (1 << aw_size[e]) * (aw_len[e] + 1);
    slot = free_b();
    if (aw_lock[e] && excl_on) begin
      if (mon_use[aw_id[e]] && mon_addr[aw_id[e]] == aw_addr[e]) begin
        rsp = EXOKAY;
        $display("mem e%0d: exclusive write id=%0d at 0x%0h: the monitor matched, EXOKAY", cycle, aw_id[e], aw_addr[e]);
      end else begin
        do_write = 0;
        $display("mem e%0d: exclusive write id=%0d at 0x%0h: no monitor, OKAY and nothing written", cycle, aw_id[e], aw_addr[e]);
      end
    end
    while (!ended && n <= aw_len[e]) begin
      a = beat_addr(aw_addr[e], aw_len[e], aw_size[e], burst_used(aw_burst[e]), n);
      lanes = beat_lanes(aw_addr[e], aw_len[e], aw_size[e], burst_used(aw_burst[e]), n, BUS);
      word = (a / BUS) * BUS;
      if (a >= err_above) rsp = SLVERR;
      else if (do_write && posted && slot >= 0) begin
        p_data[slot][n] = w_data[w_head]; p_strb[slot][n] = w_strb[w_head];
      end else if (do_write) begin
        for (int l = 0; l < BUS; l++)
          if ((w_strb[w_head][l] || ignore_strobes) && word + l < DEPTH) begin
            mem[word + l] = w_data[w_head][8*l +: 8];
            if (trace) $display("mem e%0d: beat %0d writes 0x%02h to 0x%0h (lane %0d)", cycle, n, w_data[w_head][8*l +: 8], word + l, l);
          end
      end
      ended = w_last[w_head];                      // a burst ends at its WLAST, whatever AWLEN said
      w_head = (w_head + 1) % WQ; w_count = w_count - 1;
      n = n + 1;
    end
    while (!ended) begin                           // beats past AWLEN (a broken manager) are dropped
      ended = w_last[w_head];
      w_head = (w_head + 1) % WQ; w_count = w_count - 1;
    end
    // A write clears every monitor that watches a byte it touched.
    if (do_write)
      for (int i = 0; i < (1 << ID_W); i++)
        if (mon_use[i] && mon_addr[i] < aw_addr[e] + total && aw_addr[e] < mon_addr[i] + mon_bytes[i]) mon_use[i] = 0;
    if (slot >= 0) begin
      b_use[slot] = 1; b_id[slot] = aw_id[e]; b_rsp[slot] = rsp; b_seq[slot] = seq; seq = seq + 1;
      b_at[slot] = cycle + latency_of(aw_addr[e], wr_latency);
      if (posted && do_write) begin
        p_pending[slot] = 1; p_addr[slot] = aw_addr[e]; p_len[slot] = n - 1; p_size[slot] = aw_size[e]; p_burst[slot] = aw_burst[e];
      end
    end
  endtask

  // A posted write reaches the memory when its response goes out.
  task automatic apply_posted(input int i);
    int unsigned a, word;
    for (int n = 0; n <= p_len[i]; n++) begin
      a = beat_addr(p_addr[i], p_len[i], p_size[i], burst_used(p_burst[i]), n);
      word = (a / BUS) * BUS;
      if (a < err_above)
        for (int l = 0; l < BUS; l++)
          if ((p_strb[i][n][l] || ignore_strobes) && word + l < DEPTH) begin
            mem[word + l] = p_data[i][n][8*l +: 8];
            if (trace) $display("mem e%0d: posted beat %0d writes 0x%02h to 0x%0h (lane %0d)", cycle, n, p_data[i][n][8*l +: 8], word + l, l);
          end
    end
    p_pending[i] = 0;
  endtask

  int pick, extra;
  always @(posedge aclk) begin
    cycle = cycle + 1;
    if (!aresetn) begin
      aw_head = 0; aw_tail = 0; aw_count = 0; w_head = 0; w_tail = 0; w_count = 0; w_bursts = 0;
      for (int i = 0; i < N; i++) begin b_use[i] = 0; r_use[i] = 0; end
      b_driving = 0; r_driving = 0; r_cur = -1;
      awready <= 0; wready <= 0; arready <= 0; bvalid <= 0; rvalid <= 0;
    end else begin
      // -- AW: take a request while there is room --
      if (awvalid && awready) begin
        aw_id[aw_tail] = awid; aw_addr[aw_tail] = awaddr; aw_len[aw_tail] = awlen; aw_size[aw_tail] = awsize;
        aw_burst[aw_tail] = awburst; aw_lock[aw_tail] = awlock;
        aw_tail = (aw_tail + 1) % N; aw_count = aw_count + 1;
      end
      // -- W: take a beat while there is room --
      if (wvalid && wready) begin
        w_data[w_tail] = wdata; w_strb[w_tail] = wstrb; w_last[w_tail] = wlast;
        w_tail = (w_tail + 1) % WQ; w_count = w_count + 1;
        if (wlast) w_bursts = w_bursts + 1;
      end
      // -- a complete burst with its request: write it and schedule B --
      if (aw_count > 0 && w_bursts > 0) begin
        write_burst(aw_head);
        aw_head = (aw_head + 1) % N; aw_count = aw_count - 1; w_bursts = w_bursts - 1;
        early_done = 0;
      end else if (early_b && !early_done && w_count > 0 && w_bursts == 0) begin
        // The broken twin: a response as soon as the first write beat arrived, before WLAST and,
        // when the data came first, before the address.
        pick = free_b();
        if (pick >= 0) begin
          b_use[pick] = 1; b_id[pick] = (aw_count > 0) ? aw_id[aw_head] : awid; b_rsp[pick] = OKAY; b_seq[pick] = seq; seq = seq + 1; b_at[pick] = cycle;
          early_done = 1;
        end
      end
      // -- B: finish a handshake, then put the next response on the wires --
      if (b_driving && bready) b_driving = 0;
      if (!b_driving) begin
        pick = pick_b();
        if (pick >= 0) begin
          if (p_pending[pick]) apply_posted(pick);
          b_driving = 1; bid <= b_id[pick]; bresp <= b_rsp[pick]; b_use[pick] = 0;
        end
      end
      bvalid <= b_driving;
      // -- AR: take a request while there is room --
      if (arvalid && arready) begin
        pick = free_r();
        if (pick >= 0) begin
          r_use[pick] = 1; r_id[pick] = arid; r_addr[pick] = araddr; r_len[pick] = arlen; r_size[pick] = arsize; r_burst[pick] = arburst;
          r_lock[pick] = arlock; r_beat[pick] = 0; r_seq[pick] = seq; seq = seq + 1; r_served[pick] = -1;
          r_at[pick] = cycle + latency_of(araddr, rd_latency);
          if (arlock && excl_on) begin
            mon_use[arid] = 1; mon_addr[arid] = araddr; mon_bytes[arid] = (1 << arsize) * (arlen + 1);
            $display("mem e%0d: exclusive read id=%0d at 0x%0h: monitor set", cycle, arid, araddr);
          end
        end
      end
      // -- R: finish a handshake, then put the next beat on the wires --
      if (r_driving && !rready && drop_hold) rdata <= rdata + 1;   // the broken twin: data not held
      if (r_driving && rready) begin
        r_driving = 0;
        if (r_beat[r_cur] > r_len[r_cur]) begin r_use[r_cur] = 0; r_cur = -1; end
        else if (interleave) r_cur = -1;
      end
      if (!r_driving) begin
        pick = (r_cur >= 0) ? r_cur : pick_r();
        if (pick >= 0) begin
          r_cur = pick; r_driving = 1; r_served[pick] = cycle;
          extra = r_beat[pick];
          rid <= r_id[pick];
          rdata <= read_word(beat_addr(r_addr[pick], r_len[pick], r_size[pick], burst_used(r_burst[pick]), extra));
          rresp <= (beat_addr(r_addr[pick], r_len[pick], r_size[pick], burst_used(r_burst[pick]), extra) >= err_above) ? SLVERR
                 : ((r_lock[pick] && excl_on) ? EXOKAY : OKAY);
          rlast <= (extra == r_len[pick]);
          r_beat[pick] = extra + 1;
        end
      end
      rvalid <= r_driving;
      awready <= (aw_count < N - 1);
      wready  <= (w_count < WQ - 2);
      arready <= 1;
    end
  end
endmodule

Read included file: axi_checker.sv

`timescale 1ns/1ns
// axi_checker.sv: the rules of an AXI4 interface, checked at every rising edge (read-only).
// Each broken rule is named with the channel and the edge where it was seen:
//   reset      a VALID is 1 while reset is active;
//   hold       a VALID dropped before its READY: the offer was withdrawn;
//   stable     a channel's payload changed while its offer waited;
//   known      a payload is x while its VALID is 1;
//   len        a FIXED or WRAP burst longer than 16 beats;
//   wrap       a WRAP burst whose length is not 2, 4, 8 or 16 beats or whose address is not aligned;
//   boundary   a burst that crosses a 4 KB boundary;
//   size       a transfer wider than the data bus;
//   strobe     a write strobe on a lane the beat does not address;
//   wlast      WLAST on the wrong beat (not AWLEN), or missing after it;
//   rlast      RLAST on the wrong beat of the oldest read with that ID, or missing after it;
//   border     BVALID before any outstanding write has its last beat, or before its AW;
//   bid, rid   a response ID with no outstanding request of that ID;
//   exokay     EXOKAY for a request that was not exclusive;
//   exclusive  an exclusive request whose bytes are not a power of two up to 128, or not aligned to them.
// The rules no checker can see on the wires (VALID must not wait for READY; same-ID responses
// in the order of their requests) are checked by the data the tasks compare (lessons P2.2, P2.10).
module axi_checker #(parameter int DATA_W = 32, parameter int ID_W = 4) (
  input logic              aclk,
  input logic              aresetn,
  input logic [ID_W-1:0]   awid,
  input logic [31:0]       awaddr,
  input logic [7:0]        awlen,
  input logic [2:0]        awsize,
  input logic [1:0]        awburst,
  input logic              awlock,
  input logic              awvalid,
  input logic              awready,
  input logic [DATA_W-1:0] wdata,
  input logic [DATA_W/8-1:0] wstrb,
  input logic              wlast,
  input logic              wvalid,
  input logic              wready,
  input logic [ID_W-1:0]   bid,
  input logic [1:0]        bresp,
  input logic              bvalid,
  input logic              bready,
  input logic [ID_W-1:0]   arid,
  input logic [31:0]       araddr,
  input logic [7:0]        arlen,
  input logic [2:0]        arsize,
  input logic [1:0]        arburst,
  input logic              arlock,
  input logic              arvalid,
  input logic              arready,
  input logic [ID_W-1:0]   rid,
  input logic [DATA_W-1:0] rdata,
  input logic [1:0]        rresp,
  input logic              rlast,
  input logic              rvalid,
  input logic              rready
);
  import axi_pkg::*;
  localparam int BUS = DATA_W / 8;
  localparam int Q = 64;
  int cycle = -1, writes = 0, reads = 0, stalls = 0, broken = 0;
  logic [DATA_W-1:0] used;

  function void report(input string rule, input string what);
    broken++;
    $display("RULE %s broken at edge %0d: %s", rule, cycle, what);
  endfunction

  // Previous values of every channel, for hold and stable.
  logic p_awv = 0, p_awr = 0, p_wv = 0, p_wr = 0, p_bv = 0, p_br = 0, p_arv = 0, p_arr = 0, p_rv = 0, p_rr = 0;
  logic [31:0] p_awaddr, p_araddr;
  logic [7:0] p_awlen, p_arlen;
  logic [2:0] p_awsize, p_arsize;
  logic [1:0] p_awburst, p_arburst, p_bresp, p_rresp;
  logic [ID_W-1:0] p_awid, p_arid, p_bid, p_rid;
  logic [DATA_W-1:0] p_wdata, p_rdata;
  logic [BUS-1:0] p_wstrb;
  logic p_wlast, p_rlast, p_awlock, p_arlock;

  // Write requests in order (AXI4 write data follows the order of the addresses).
  int unsigned q_addr [0:Q-1];
  int q_len [0:Q-1];
  logic [2:0] q_size [0:Q-1];
  logic [1:0] q_burst [0:Q-1];
  int aw_n = 0;                 // requests accepted
  int wb_n = 0;                 // write bursts started
  int wb_done = 0;              // write bursts ended (WLAST seen)
  int w_beat = 0;               // beats so far in the current burst
  int b_n = 0;                  // responses given
  // Beats recorded for bursts that ran ahead of their AW: strobes and count, checked when AW arrives.
  logic [BUS-1:0] rec_strb [0:Q-1][0:255];
  int rec_beats [0:Q-1];
  logic rec_open [0:Q-1];
  // Outstanding requests per ID, and the read requests per ID in order.
  int aw_out [0:(1<<ID_W)-1], ar_out [0:(1<<ID_W)-1], aw_excl [0:(1<<ID_W)-1], ar_excl [0:(1<<ID_W)-1];
  int rq_len [0:(1<<ID_W)-1][0:15];
  int rq_head [0:(1<<ID_W)-1], rq_tail [0:(1<<ID_W)-1], r_beat [0:(1<<ID_W)-1];
  initial for (int i = 0; i < (1 << ID_W); i++) begin aw_out[i] = 0; ar_out[i] = 0; aw_excl[i] = 0; ar_excl[i] = 0; rq_head[i] = 0; rq_tail[i] = 0; r_beat[i] = 0; end
  initial for (int i = 0; i < Q; i++) begin rec_beats[i] = 0; rec_open[i] = 0; end

  function automatic bit pow2_le128(input int unsigned n);
    return (n == 1 || n == 2 || n == 4 || n == 8 || n == 16 || n == 32 || n == 64 || n == 128);
  endfunction

  task automatic check_request(input string ch, input int unsigned addr, input int len, input logic [2:0] size, input logic [1:0] burst, input logic lock);
    int unsigned bytes = (1 << size) * (len + 1);
    if ((burst == FIXED || burst == WRAP) && len > 15) report("len", $sformatf("%s: a %s burst of %0d beats (16 at most)", ch, burst_name(burst), len + 1));
    if (burst == WRAP && !(len == 1 || len == 3 || len == 7 || len == 15)) report("wrap", $sformatf("%s: a WRAP burst of %0d beats (2, 4, 8 or 16)", ch, len + 1));
    if (burst == WRAP && (addr % (1 << size)) != 0) report("wrap", $sformatf("%s: WRAP burst at 0x%0h is not aligned to its %0d-byte transfers", ch, addr, 1 << size));
    if (burst == 2'b11) report("len", $sformatf("%s: burst type 2'b11 is reserved", ch));
    if ((1 << size) > BUS) report("size", $sformatf("%s: %0d-byte transfers on a %0d-byte bus", ch, 1 << size, BUS));
    if (crosses_4k(addr, len, size, burst)) report("boundary", $sformatf("%s: burst at 0x%0h, %0d beats of %0d bytes, crosses a 4 KB boundary", ch, addr, len + 1, 1 << size));
    if (lock && (!pow2_le128(bytes) || (addr % bytes) != 0)) report("exclusive", $sformatf("%s: exclusive access of %0d bytes at 0x%0h (a power of two up to 128, aligned)", ch, bytes, addr));
  endtask

  task automatic check_strobe(input int k, input int n, input logic [BUS-1:0] strb);
    logic [63:0] allowed = beat_strb(q_addr[k % Q], q_len[k % Q], q_size[k % Q], q_burst[k % Q], n, BUS);
    if ((strb & ~allowed[BUS-1:0]) != 0)
      report("strobe", $sformatf("W beat %0d of write %0d: strobe %b on lanes outside %b", n, k, strb, allowed[BUS-1:0]));
  endtask

  always @(posedge aclk) begin
    cycle++;
    if (!aresetn) begin
      if (awvalid === 1 || wvalid === 1 || arvalid === 1) report("reset", "a manager VALID is 1 during reset");
      if (bvalid === 1 || rvalid === 1) report("reset", "a subordinate VALID is 1 during reset");
    end else begin
      // hold, stable and known, per channel
      if (p_awv && !p_awr && awvalid !== 1) report("hold", "AWVALID dropped before AWREADY");
      if (p_awv && !p_awr && awvalid === 1 && (awaddr !== p_awaddr || awlen !== p_awlen || awsize !== p_awsize || awburst !== p_awburst || awid !== p_awid || awlock !== p_awlock)) report("stable", "AW payload changed while the request waited");
      if (p_wv && !p_wr && wvalid !== 1) report("hold", "WVALID dropped before WREADY");
      if (p_wv && !p_wr && wvalid === 1 && (wdata !== p_wdata || wstrb !== p_wstrb || wlast !== p_wlast)) report("stable", "W payload changed while the beat waited");
      if (p_bv && !p_br && bvalid !== 1) report("hold", "BVALID dropped before BREADY");
      if (p_bv && !p_br && bvalid === 1 && (bresp !== p_bresp || bid !== p_bid)) report("stable", "B payload changed while the response waited");
      if (p_arv && !p_arr && arvalid !== 1) report("hold", "ARVALID dropped before ARREADY");
      if (p_arv && !p_arr && arvalid === 1 && (araddr !== p_araddr || arlen !== p_arlen || arsize !== p_arsize || arburst !== p_arburst || arid !== p_arid || arlock !== p_arlock)) report("stable", "AR payload changed while the request waited");
      if (p_rv && !p_rr && rvalid !== 1) report("hold", "RVALID dropped before RREADY");
      if (p_rv && !p_rr && rvalid === 1 && (rdata !== p_rdata || rresp !== p_rresp || rid !== p_rid || rlast !== p_rlast)) report("stable", "R payload changed while the beat waited");
      if (awvalid === 1 && ($isunknown(awaddr) || $isunknown(awlen) || $isunknown(awsize) || $isunknown(awburst) || $isunknown(awid))) report("known", "AW payload is x while AWVALID is 1");
      if (wvalid === 1 && ($isunknown(wstrb) || $isunknown(wlast))) report("known", "W strobe or last is x while WVALID is 1");
      else if (wvalid === 1) begin
        used = '0;
        for (int l = 0; l < BUS; l++) if (wstrb[l] === 1) used[8*l +: 8] = 8'hff;
        if ($isunknown(wdata & used)) report("known", "W data is x on a strobed lane while WVALID is 1");
      end
      if (arvalid === 1 && ($isunknown(araddr) || $isunknown(arlen) || $isunknown(arsize) || $isunknown(arburst) || $isunknown(arid))) report("known", "AR payload is x while ARVALID is 1");
      if (bvalid === 1 && ($isunknown(bresp) || $isunknown(bid))) report("known", "B payload is x while BVALID is 1");
      if (rvalid === 1 && ($isunknown(rresp) || $isunknown(rid) || $isunknown(rlast))) report("known", "R payload is x while RVALID is 1");
      if ((awvalid === 1 && awready !== 1) || (wvalid === 1 && wready !== 1) || (arvalid === 1 && arready !== 1) ||
          (bvalid === 1 && bready !== 1) || (rvalid === 1 && rready !== 1)) stalls++;
      // AW accepted
      if (awvalid === 1 && awready === 1) begin
        check_request("AW", awaddr, awlen, awsize, awburst, awlock);
        q_addr[aw_n % Q] = awaddr; q_len[aw_n % Q] = awlen; q_size[aw_n % Q] = awsize; q_burst[aw_n % Q] = awburst;
        aw_out[awid]++; if (awlock) aw_excl[awid]++;
        // beats of this write that arrived before its address: check them now
        if (rec_beats[aw_n % Q] > 0) begin
          for (int n = 0; n < rec_beats[aw_n % Q]; n++) check_strobe(aw_n, n, rec_strb[aw_n % Q][n]);
          if (!rec_open[aw_n % Q] && rec_beats[aw_n % Q] != awlen + 1)
            report("wlast", $sformatf("write %0d sent %0d beats before its AW said AWLEN=%0d", aw_n, rec_beats[aw_n % Q], awlen));
          if (!rec_open[aw_n % Q]) rec_beats[aw_n % Q] = 0;
        end
        aw_n++;
      end
      // W beat accepted
      if (wvalid === 1 && wready === 1) begin
        if (w_beat == 0) begin wb_n++; rec_beats[(wb_n - 1) % Q] = 0; rec_open[(wb_n - 1) % Q] = 1; end
        if (wb_n <= aw_n) begin
          check_strobe(wb_n - 1, w_beat, wstrb);
          if (wlast === 1 && w_beat != q_len[(wb_n - 1) % Q]) report("wlast", $sformatf("WLAST on beat %0d of write %0d, AWLEN=%0d", w_beat, wb_n - 1, q_len[(wb_n - 1) % Q]));
          if (wlast !== 1 && w_beat == q_len[(wb_n - 1) % Q]) report("wlast", $sformatf("beat %0d of write %0d is AWLEN=%0d but WLAST is 0", w_beat, wb_n - 1, q_len[(wb_n - 1) % Q]));
        end else begin
          rec_strb[(wb_n - 1) % Q][w_beat] = wstrb;
        end
        rec_beats[(wb_n - 1) % Q] = w_beat + 1;
        w_beat++;
        if (wlast === 1) begin w_beat = 0; wb_done++; rec_open[(wb_n - 1) % Q] = 0; if (wb_n <= aw_n) rec_beats[(wb_n - 1) % Q] = 0; end
      end
      // B offered or accepted
      if (bvalid === 1 && !p_bv) begin
        if (b_n >= aw_n && b_n >= wb_done) report("border", "BVALID with no write to answer: neither an AW nor a WLAST is outstanding");
        else if (b_n >= wb_done) report("border", "BVALID before the last beat of the write it answers");
        else if (b_n >= aw_n) report("border", "BVALID before the AW of the write it answers was accepted");
      end
      if (bvalid === 1 && bready === 1) begin
        if (aw_out[bid] == 0) report("bid", $sformatf("B with id %0d, which has no outstanding write", bid));
        else begin
          aw_out[bid]--; writes++;
          if (bresp === EXOKAY && aw_excl[bid] == 0) report("exokay", $sformatf("EXOKAY for write id %0d, which was not exclusive", bid));
          if (aw_excl[bid] > 0 && aw_excl[bid] > aw_out[bid]) aw_excl[bid] = aw_out[bid];
        end
        b_n++;
      end
      // AR accepted
      if (arvalid === 1 && arready === 1) begin
        check_request("AR", araddr, arlen, arsize, arburst, arlock);
        rq_len[arid][rq_tail[arid]] = arlen; rq_tail[arid] = (rq_tail[arid] + 1) % 16;
        ar_out[arid]++; if (arlock) ar_excl[arid]++;
      end
      // R beat accepted
      if (rvalid === 1 && rready === 1) begin
        if (ar_out[rid] == 0) report("rid", $sformatf("R with id %0d, which has no outstanding read", rid));
        else begin
          if (rlast === 1 && r_beat[rid] != rq_len[rid][rq_head[rid]])
            report("rlast", $sformatf("RLAST on beat %0d of the oldest read with id %0d, whose ARLEN is %0d", r_beat[rid], rid, rq_len[rid][rq_head[rid]]));
          if (rlast !== 1 && r_beat[rid] == rq_len[rid][rq_head[rid]])
            report("rlast", $sformatf("beat %0d of the oldest read with id %0d is its ARLEN but RLAST is 0", r_beat[rid], rid));
          if (rresp === EXOKAY && ar_excl[rid] == 0) report("exokay", $sformatf("EXOKAY for read id %0d, which was not exclusive", rid));
          r_beat[rid]++;
          if (rlast === 1) begin
            r_beat[rid] = 0; rq_head[rid] = (rq_head[rid] + 1) % 16; ar_out[rid]--; reads++;
            if (ar_excl[rid] > ar_out[rid]) ar_excl[rid] = ar_out[rid];
          end
        end
      end
    end
    p_awv = (awvalid === 1); p_awr = (awready === 1); p_wv = (wvalid === 1); p_wr = (wready === 1);
    p_bv = (bvalid === 1); p_br = (bready === 1); p_arv = (arvalid === 1); p_arr = (arready === 1);
    p_rv = (rvalid === 1); p_rr = (rready === 1);
    p_awaddr = awaddr; p_awlen = awlen; p_awsize = awsize; p_awburst = awburst; p_awid = awid; p_awlock = awlock;
    p_wdata = wdata; p_wstrb = wstrb; p_wlast = wlast; p_bresp = bresp; p_bid = bid;
    p_araddr = araddr; p_arlen = arlen; p_arsize = arsize; p_arburst = arburst; p_arid = arid; p_arlock = arlock;
    p_rdata = rdata; p_rresp = rresp; p_rid = rid; p_rlast = rlast;
  end
  final $display("checker: %0d writes, %0d reads, %0d stalled edges, %0d rules broken", writes, reads, stalls, broken);
endmodule

Read included file: axi_tasks.svh

// axi_tasks.svh: the manager side of the bench, as tasks for the stimulus (read-only).
// Data for a write burst goes in wd[0], wd[1], ... (one entry per beat, the lowest byte at the
// lowest address); the data of a read comes back in rd[0], rd[1], ... with its responses in rr[].
// Every task prints the beat log: one line per handshake, with the edge where it happened.
// `cycle` counts rising edges from 0.
int cycle = -1;
always @(posedge aclk) cycle = cycle + 1;

logic [63:0] wd [0:255];
logic [63:0] rd [0:255];
logic [1:0]  rr [0:255];
logic [63:0] rdq [0:15][0:255];     // read data per ID, for reads collected out of order
logic [1:0]  rrq [0:15][0:255];
int          rdn [0:15];            // beats received per ID
logic [1:0]  last_bresp = 0;
int          last_beats = 0;
// What the task is driving right now, for the waveform scenes: the address and lanes of the beat.
int unsigned beat_a = 0;
logic [7:0]  beat_m = 0;
// quiet = 1 silences the beat log (a predict item can then ask for a dump line instead).
bit          quiet = 0;
// Strobe override: when strb_force is 1, every write beat uses strb_val as it is.
bit          strb_force = 0;
logic [7:0]  strb_val = 8'hff;
// Outstanding read requests per ID, so the tasks know the lanes of the beats that come back.
int unsigned arq_addr [0:15][0:7];
int          arq_len [0:15][0:7];
logic [2:0]  arq_size [0:15][0:7];
logic [1:0]  arq_burst [0:15][0:7];
int          arq_head [0:15], arq_tail [0:15];
initial for (int i = 0; i < 16; i++) begin arq_head[i] = 0; arq_tail[i] = 0; rdn[i] = 0; end
// READY patterns for the response channels: bit (cycle % 16) of the pattern drives the signal.
bit          rpat_on = 0, bpat_on = 0;
logic [15:0] rpat = 16'hffff, bpat = 16'hffff;
always @(posedge aclk) begin
  #1;
  if (rpat_on) rready = rpat[cycle % 16];
  if (bpat_on) bready = bpat[cycle % 16];
end

// A text waveform for the lesson's trace blocks: with watch = 1, one line per rising edge with the
// values sampled at that edge (cycle k of a trace is what edge k sees).
bit watch = 0;
int wave_edge = -1;
always @(posedge aclk) begin
  wave_edge = wave_edge + 1;
  if (watch) $display("wave e%0d: aw=%b%b w=%b%b b=%b%b ar=%b%b r=%b%b awaddr=%h wdata=%h wstrb=%b wlast=%b bid=%h bresp=%b araddr=%h rid=%h rdata=%h rresp=%b rlast=%b",
                      wave_edge, awvalid, awready, wvalid, wready, bvalid, bready, arvalid, arready, rvalid, rready,
                      awaddr, wdata, wstrb, wlast, bid, bresp, araddr, rid, rdata, rresp, rlast);
end

// Drive RREADY (ch = 0) or BREADY (ch = 1) from a 16-bit pattern; 16'hffff restores always ready.
task automatic ready_pattern(input int ch, input logic [15:0] pat);
  if (ch == 0) begin rpat = pat; rpat_on = 1; rready = pat[cycle % 16]; end
  else begin bpat = pat; bpat_on = 1; bready = pat[cycle % 16]; end
endtask

// The write address channel: offer the request and hold it until it is taken.
task automatic aw_issue(input logic [ID_W-1:0] id, input int unsigned addr, input int len, input logic [2:0] size,
                        input logic [1:0] burst, input logic lock = 0);
  awid = id; awaddr = addr; awlen = len[7:0]; awsize = size; awburst = burst; awlock = lock; awvalid = 1;
  do @(posedge aclk); while (!awready);
  #1 if (!quiet) $display("e%0d AW id=%0d addr=0x%0h len=%0d size=%0d %0s%0s", cycle, id, addr, len, size, burst_name(burst), lock ? " exclusive" : "");
  awvalid = 0; awaddr = 'x; awlen = 'x; awsize = 'x; awburst = 'x; awid = 'x; awlock = 0;
endtask

// The write data channel: the beats of one burst from wd[first..], each placed in its lanes.
task automatic w_burst(input int unsigned addr, input int len, input logic [2:0] size, input logic [1:0] burst, input int first = 0);
  logic [15:0] lanes;
  for (int n = 0; n <= len; n++) begin
    lanes = beat_lanes(addr, len, size, burst, n, BUS_BYTES);
    beat_a = beat_addr(addr, len, size, burst, n);
    beat_m = strb_force ? strb_val : beat_strb(addr, len, size, burst, n, BUS_BYTES);
    wdata = wd[first + n] << (8 * lanes[7:0]);
    wstrb = beat_m[BUS_BYTES-1:0];
    wlast = (n == len);
    wvalid = 1;
    do @(posedge aclk); while (!wready);
    #1 if (!quiet) $display("e%0d W  beat %0d data=0x%0h strb=%b last=%0d  addr 0x%0h lanes %0d-%0d", cycle, n, wdata, wstrb, wlast, beat_a, lanes[7:0], lanes[15:8]);
  end
  wvalid = 0; wdata = 'x; wstrb = 'x; wlast = 0; beat_m = 0;
endtask

// Wait for the write response of one transaction with this ID.
task automatic b_wait(input logic [ID_W-1:0] id);
  do @(posedge aclk); while (!(bvalid && bready && bid == id));
  last_bresp = bresp;                       // sampled at the edge, before the subordinate moves on
  #1 if (!quiet) $display("e%0d B  id=%0d %0s", cycle, id, resp_name(last_bresp));
endtask

// A complete write. order 0 offers the address, then the first beat one cycle later whether or
// not the address has been taken yet (a manager must never make WVALID wait for AWREADY); 1 offers
// the beats first and the address after beat 0; 2 offers the address and beat 0 in the same cycle.
// Returns after B, with the response in last_bresp.
task automatic axi_write(input logic [ID_W-1:0] id, input int unsigned addr, input int len, input logic [2:0] size,
                         input logic [1:0] burst, input int order = 0, input logic lock = 0);
  case (order)
    1: fork
         w_burst(addr, len, size, burst);
         begin @(posedge aclk); #1 aw_issue(id, addr, len, size, burst, lock); end
       join
    2: fork
         aw_issue(id, addr, len, size, burst, lock);
         w_burst(addr, len, size, burst);
       join
    default: fork
         aw_issue(id, addr, len, size, burst, lock);
         begin @(posedge aclk); #1 w_burst(addr, len, size, burst); end
       join
  endcase
  b_wait(id);
endtask

// The read address channel: offer the request and remember it for the beats that come back.
task automatic ar_issue(input logic [ID_W-1:0] id, input int unsigned addr, input int len, input logic [2:0] size,
                        input logic [1:0] burst, input logic lock = 0);
  arq_addr[id][arq_tail[id]] = addr; arq_len[id][arq_tail[id]] = len; arq_size[id][arq_tail[id]] = size;
  arq_burst[id][arq_tail[id]] = burst; arq_tail[id] = (arq_tail[id] + 1) % 8;
  arid = id; araddr = addr; arlen = len[7:0]; arsize = size; arburst = burst; arlock = lock; arvalid = 1;
  do @(posedge aclk); while (!arready);
  #1 if (!quiet) $display("e%0d AR id=%0d addr=0x%0h len=%0d size=%0d %0s%0s", cycle, id, addr, len, size, burst_name(burst), lock ? " exclusive" : "");
  arvalid = 0; araddr = 'x; arlen = 'x; arsize = 'x; arburst = 'x; arid = 'x; arlock = 0;
endtask

// Collect read beats until n transactions have ended (their RLAST). Each beat lands in rdq[rid][k]
// with only the bytes of the transfer (lane-shifted down), and rd[] holds the last transaction.
task automatic r_collect(input int n);
  int done = 0, h;
  logic [15:0] lanes;
  logic [63:0] bytes;
  logic [ID_W-1:0] id;
  logic [DATA_W-1:0] data;
  logic [1:0] resp;
  logic last;
  while (done < n) begin
    do @(posedge aclk); while (!(rvalid && rready));
    id = rid; data = rdata; resp = rresp; last = rlast;   // sampled at the edge, before the subordinate moves on
    h = arq_head[id];
    lanes = beat_lanes(arq_addr[id][h], arq_len[id][h], arq_size[id][h], arq_burst[id][h], rdn[id], BUS_BYTES);
    beat_a = beat_addr(arq_addr[id][h], arq_len[id][h], arq_size[id][h], arq_burst[id][h], rdn[id]);
    beat_m = beat_strb(arq_addr[id][h], arq_len[id][h], arq_size[id][h], arq_burst[id][h], rdn[id], BUS_BYTES);
    bytes = (data >> (8 * lanes[7:0])) & ((64'h1 << (8 * (lanes[15:8] - lanes[7:0] + 1))) - 1);
    rdq[id][rdn[id]] = bytes; rrq[id][rdn[id]] = resp;
    #1 if (!quiet) $display("e%0d R  id=%0d beat %0d data=0x%0h %0s%0s  addr 0x%0h lanes %0d-%0d", cycle, id, rdn[id], bytes, resp_name(resp),
                last ? " last" : "", beat_a, lanes[7:0], lanes[15:8]);
    rdn[id] = rdn[id] + 1;
    if (last) begin
      for (int k = 0; k < rdn[id]; k++) begin rd[k] = rdq[id][k]; rr[k] = rrq[id][k]; end
      last_beats = rdn[id]; rdn[id] = 0; arq_head[id] = (h + 1) % 8; done = done + 1;
    end
  end
  beat_m = 0;
endtask

// A complete read: AR, then every beat, into rd[] and rr[].
task automatic axi_read(input logic [ID_W-1:0] id, input int unsigned addr, input int len, input logic [2:0] size,
                        input logic [1:0] burst, input logic lock = 0);
  ar_issue(id, addr, len, size, burst, lock);
  r_collect(1);
endtask

// The table of a burst before it runs: the address, lanes and strobe of every beat.
task automatic beat_table(input int unsigned addr, input int len, input logic [2:0] size, input logic [1:0] burst);
  logic [15:0] lanes;
  logic [63:0] s;
  int unsigned a;
  $display("burst at 0x%0h: %0d beat%0s of %0d byte%0s, %0s, bus %0d bytes", addr, len + 1, len ? "s" : "", 1 << size, size ? "s" : "",
           burst_name(burst), BUS_BYTES);
  $display("  beat  address  lanes  strobe");
  for (int n = 0; n <= len; n++) begin
    lanes = beat_lanes(addr, len, size, burst, n, BUS_BYTES);
    s = beat_strb(addr, len, size, burst, n, BUS_BYTES);
    a = beat_addr(addr, len, size, burst, n);
    $display("  %4d  0x%05h  %0d-%0d    %b", n, a[19:0], lanes[7:0], lanes[15:8], s[BUS_BYTES-1:0]);
  end
  if (crosses_4k(addr, len, size, burst)) $display("  this burst crosses a 4 KB boundary");
endtask

// One byte of the memory that owns an address (the fabric's second memory above 0x8000).
function automatic logic [7:0] mem_byte(input int unsigned a);
`ifdef AXI_MEM1
  if (a >= 32'h8000) return `AXI_MEM1.mem[a];
`endif
  return `AXI_MEM.mem[a];
endfunction
task automatic set_byte(input int unsigned a, input logic [7:0] v);
`ifdef AXI_MEM1
  if (a >= 32'h8000) `AXI_MEM1.mem[a] = v;
  else `AXI_MEM.mem[a] = v;
`else
  `AXI_MEM.mem[a] = v;
`endif
endtask

// The memory, n bytes from addr, one bus word per group.
task automatic dump(input int unsigned addr, input int n);
  string line;
  int unsigned a = (addr / 16) * 16;
  while (a < addr + n) begin
    line = $sformatf("0x%05h ", a[19:0]);
    for (int i = 0; i < 16; i++) begin
      if (i % BUS_BYTES == 0) line = {line, " "};
      line = {line, $sformatf(" %02h", mem_byte(a + i))};
    end
    $display("%s", line);
    a = a + 16;
  end
endtask

// Fill n bytes from addr with first, first+1, ... so untouched bytes stay recognisable.
task automatic mem_fill(input int unsigned addr, input int n, input logic [7:0] first = 8'h00);
  for (int i = 0; i < n; i++) set_byte(addr + i, first + i[7:0]);
endtask

// Drive nothing for n cycles.
task automatic idle(input int n);
  repeat (n) @(posedge aclk);
  #1;
endtask

ConceptA bridge converts a 4-beat write burst into four AXI4-Lite writes. Three of them answer OKAY and the third answers SLVERR. What does the manager receive?

One B response, SLVERR, because an error in any generated write is keptFour B responses, one per generated write, in the order they were issuedOne B response, OKAY, because most of the generated writes succeededOne B response per failing write, so a single SLVERR and nothing for the others

ConceptWhy can an AXI4-Lite subordinate be wired straight to a full AXI manager in some systems?

Because the interconnect always converts bursts before any subordinate sees themBecause the subordinate reflects AWID and ARID and the system guarantees Lite-only transactionsBecause WLAST and RLAST are optional on every AXI interfaceBecause full AXI managers never issue bursts to register addresses

ConceptWhich of these is an AXI3 feature that AXI4 removed?

The 4 KB boundary rule for burstsINCR bursts of up to 256 transfersWrite data interleaving with the WID signalNarrow transfers with write strobes

ConceptWhat does AXI5's credited transport change about a channel?

VALID goes away; the receiver pulls transfers whenever it has a credit to spendBoth VALID and READY stay, with CRDT as a third signal that pauses them during clock gatingNothing on the wires; credits are a bookkeeping convention inside the interconnectREADY goes away; the receiver gives credits and the sender asserts VALID only while it holds one

Remember

AXI4-Lite is one transfer per transaction at the full bus width (32 or 64 bits), Non-modifiable and Non-bufferable, with no IDs and no exclusives. The handshakes, the strobes, AxPROT and the responses stay; the burst signals, the IDs, WLAST and RLAST are gone.
A Lite subordinate on a full AXI interface must reflect AWID and ARID, and the system must guarantee Lite-shaped transactions or put a bridge in between.
A converting bridge turns a burst into single transfers at the addresses of the burst type and combines their responses into one, any error sticky. It discards AxLOCK and AxCACHE and passes strobes and AxPROT.
AXI4 over AXI3: INCR bursts to 256, no WID and no write data interleaving, no locked transactions, the write response only after AW and the last W. AxQOS, AxREGION and the user signals are new.
AXI5 adds options: credited transport without READY, the unique ID indicator, read data chunking, parity and poison, RME address spaces and Memory Encryption Contexts. AXI5-Lite may reorder across IDs.

Practice

A Lite subordinate Fix · Medium