ASIC Point

Silicon Lab

Physical Design Problems

Build a design, hunt its bugs, or repair what fails. Every answer runs on a real simulator.

Build starts from a specification: make it work, then make it small or fast. Bug Hunt asks for the checker or the test that catches broken designs. Repair hands you a failure: find the cause, then fix the design.

Physical Design · L1

  1. L1.2.1 The smaller enable register 975 Optimize Easy Verilator
  2. L1.4.1 Finish legal cell placement 975 Implement Easy Verilator
  3. L1.6.1 The clock that reached no register 1050 Fix Easy Verilator
  4. L1.6.2 Reject an incomplete timing report 1200 Verify Medium Verilator

Physical Design · L2

  1. L2.4.1 The smallest hold repair 1050 Optimize Medium Verilator
  2. L2.7.1 Budget both sides of the block 1050 Implement Medium Verilator
  3. L2.8.1 Restore the same-edge hold check 1125 Fix Medium Verilator
  4. L2.9.1 A checker for timing and electrical limits 1200 Verify Medium Verilator

Physical Design · L3

  1. L3.1.1 A floorplan after snapping 1050 Implement Medium Verilator
  2. L3.3.1 Open a route past the macros 1125 Fix Medium Verilator
  3. L3.4.1 A connected grid with floating wells 1200 Verify Medium Verilator
  4. L3.5.1 Spend fewer straps on the grid 1050 Optimize Medium Verilator

Physical Design · L4

  1. L4.3.1 Recover wirelength after legalization 975 Implement Easy Verilator
  2. L4.3.2 Approve the placed block 1200 Verify Medium Verilator
  3. L4.4.1 Repair the slow reset tree 1125 Fix Medium Verilator
  4. L4.5.1 Close placement timing within area 1050 Optimize Medium Verilator

Physical Design · L5

  1. L5.1.1 Separate local skew from clock spread 975 Implement Easy Verilator
  2. L5.2.1 Check the clock-tree handoff 1200 Verify Medium Verilator
  3. L5.3.1 Put the external clock at its real edge 1125 Fix Medium Verilator
  4. L5.4.1 Schedule three capture clocks 1050 Optimize Medium Verilator

Physical Design · L6

  1. L6.3.1 Give the crossbar pins room 1125 Fix Medium Verilator
  2. L6.4.1 Require the routed checks together 1200 Verify Medium Verilator
  3. L6.6.1 Compute a clock-pin antenna budget 975 Implement Easy Verilator
  4. L6.6.2 Protect the routes with fewer diodes 1050 Optimize Medium Verilator

Physical Design · L7

  1. L7.1.1 Make the hold repair survive four corners 1050 Implement Medium Verilator
  2. L7.3.1 Check the base cells after an ECO 1200 Verify Medium Verilator
  3. L7.5.1 Reconnect the selector without new base cells 1125 Fix Medium Verilator
  4. L7.5.2 Improve cold-corner timing within area 1050 Optimize Medium Verilator

Physical Design · L8

  1. L8.1.1 Keep the FIFO crossings visible 1050 Implement Medium Verilator
  2. L8.2.1 Diagnose hold before adding cells 1125 Fix Medium Verilator
  3. L8.3.1 Route the fixed-die register file within area 1050 Optimize Medium Verilator
  4. L8.4.1 Reject an overstated datasheet 1200 Verify Medium Verilator