Fix a completer that answers a byte write by rewriting all four bytes of the word.
Hardware context: An APB register written one byte lane at a time. Fix a completer that writes every lane regardless of PSTRB.
This is a Fix problem: the completer in the editor has one realistic defect. Find it and fix it.
A driver sets one byte of a word with a single-lane write, and the other three bytes of the word go to whatever the data bus held there. The strobes on the wire were right: PSTRB had one bit set, for the lane that carried the byte. The completer never looked at them (lesson P3.5; IHI 0024E 3.2: PSTRB bit n marks byte lane n of PWDATA as valid, so a lane whose strobe is 0 must not be written).
The fixture runs scripts of writes with full, sparse and empty strobes and reads the words back, together with the completer's write counter. Make a byte write change one byte.
Signals in the Timeline
| Signal | Width | Role |
|---|---|---|
n | 8 | input of each check |
script_first | 144 | input of each check |
script_last | 144 | input of each check |
Full specification
module apb_strb (
input logic pclk,
input logic presetn, // active-low, asynchronous
input logic psel,
input logic penable,
input logic pwrite,
input logic [7:0] paddr, // byte address of the register
input logic [31:0] pwdata,
input logic [3:0] pstrb,
output logic pready,
output logic [31:0] prdata,
output logic pslverr
);
// 16 bytes of RAM and a write counter
endmodule
| Address | Read | Write |
|---|---|---|
| 0x00, 0x04, 0x08, 0x0c | the word | byte l takes PWDATA bits 8l+7 to 8l where PSTRB bit l is 1; other bytes keep their value |
| 0x10 WCOUNT | the writes completed since reset, a write with PSTRB 0000 included | ignored, but counted |
| other | 0 | ignored, but counted |
Sparse strobes such as 0101 are legal, and so is a write with every strobe low: it changes no byte and still completes. Lanes are fixed: PSTRB[n] belongs to PWDATA[8n+7:8n] whatever the address.
The result is {transfers_done[3:0], wait_cycles[5:0], error_bits[5:0], read_before_last[31:0], last_read[31:0]}: the transfers completed, the wait cycles the requester saw, one bit per transfer that ended with PSLVERR (bit i for transfer i), and the data of the last two reads that completed without an error.
Examples
Example 1
One Byte into Lane 1- Input
write 0x04 = 44332211; write 0x04 = 0000ee00 strb 0010; read 0x04
- Output
transfers_done = 3, wait_cycles = 0, error_bits = 'b000000, read_before_last = 0x0, last_read = 0x4433ee11
The word holds 44332211; strobe 0010 with ee in lane 1 makes it 4433ee11. The shipped block writes 0000ee00.
Example 2
A Halfword into the Upper Lanes- Input
write 0x08 = 44332211; write 0x08 = beef0000 strb 1100; read 0x08
- Output
transfers_done = 3, wait_cycles = 0, error_bits = 'b000000, read_before_last = 0x0, last_read = 0xbeef2211
Strobe 1100 with beef in lanes 3 and 2: the word becomes beef2211.
Example 3
A Sparse Write- Input
write 0x00 = 11111111; write 0x00 = aabbccdd strb 0101; read 0x00
- Output
transfers_done = 3, wait_cycles = 0, error_bits = 'b000000, read_before_last = 0x0, last_read = 0x11bb11dd
Strobe 0101 takes dd into lane 0 and bb into lane 2; lanes 1 and 3 keep 11: the word reads 11bb11dd.
Constraints and Contract
- Addresses are word aligned; the requester drives PSTRB 0000 on reads, as the protocol requires.
- Keep the module name and the ports; the counter and the reads are correct as shipped.
Hints
Hint 1
Run the first example: 0x04 should read 4433ee11 and the shipped block reads 0000ee00.
Hint 2
Merge, do not replace: byte l of the word changes only when PSTRB bit l is 1.
Hint 3
The loop over the four lanes is already there; it is missing its condition.
What the grader checks: The completer runs six directed scripts and eight seeded ones; the words read back and the write counter are compared with a byte-merge model. Passing shows the strobe rule holds for these writes; unaligned addresses are outside this problem.
14 checks on Icarus Verilog · browser. Run the examples first, then check the full regression. The suite is local and inspectable. A passing result establishes the tested cases, not a proof for all possible inputs.
See all 1 steps and the final capstone