ASIC Point Explore

Silicon Lab

Protocols Problems

Build a design, hunt its bugs, or repair what fails. Every answer runs on a real simulator.

Build starts from a specification: make it work, then make it small or fast. Bug Hunt asks for the checker or the test that catches broken designs. Repair hands you a failure: find the cause, then fix the design.

01

On-Chip Interconnect Protocols

Bus basics, then the AMBA buses: AXI, APB and AHB.

26 problems

Protocols · P1 Protocol Fundamentals

  1. P1.3.1 Implement a Sink 1125 Implement Medium Browser
  2. P1.4.1 Beats into Transactions 750 Implement Easy Browser
  3. P1.6.2 A Credit Counter 975 Implement Medium Browser
  4. P1.7.1 A Scoreboard Keyed by Tag 1200 Implement Medium Browser
  5. P1.9.1 A Round-Robin Arbiter Model 975 Implement Medium Browser
  6. P1.11.5 A Monitor for the Link 975 Implement Medium Browser

Protocols · P2 AXI

  1. P2.5.1 An Issuer with N Outstanding 1125 Implement Medium Browser
  2. P2.6.1 The Address of Every Beat 1200 Implement Medium Browser
  3. P2.7.1 The Lane Mapper 1050 Implement Medium Browser
  4. P2.8.1 A Byte-Accurate Write Memory 1425 Implement Hard Browser
  5. P2.11.1 An ID-Keyed Scoreboard 1200 Implement Medium Browser
  6. P2.13.1 An Exclusive Monitor 1200 Implement Medium Browser
  7. P2.17.1 The AXI Monitor 1350 Implement Hard UVM
  8. P2.18.6 A Beat-to-Transaction Monitor 1425 Implement Hard Browser

Protocols · P3 APB

  1. P3.2.2 An APB Requester 1275 Implement Medium Browser
  2. P3.2.1 An APB Register Block 1350 Implement Hard Browser
  3. P3.6.1 Decoder and Read Mux 975 Implement Medium Browser
  4. P3.7.1 The Bridge's APB Side 1425 Implement Hard Browser
  5. P3.9.1 The APB Monitor 1200 Implement Medium UVM
  6. P3.9.2 The Register Adapter 1275 Implement Medium UVM

Protocols · P4 AHB

  1. P4.2.1 A Zero-Wait AHB Subordinate 1200 Implement Medium Browser
  2. P4.6.1 The Beat Generator 1200 Implement Medium Browser
  3. P4.8.2 Decoder and Default Subordinate 1125 Implement Medium Browser
  4. P4.9.1 An Exclusive Access Monitor 1350 Implement Hard Browser
  5. P4.11.1 The AHB Monitor 1425 Implement Hard UVM
  6. P4.12.4 An AHB-to-APB Bridge 1350 Implement Hard Browser
02

Peripheral & Serial Interface Protocols

Serial fundamentals, then UART, SPI and QSPI, I2C and I3C.

17 problems

Module P6 · Protocols · P6 UART

  1. P6.2.1 Encode a UART Frame 825 Implement Easy Browser
  2. P6.4.1 A Receiver That Survives the Sweep 1650 Implement Hard Browser
  3. P6.6.1 RTS and CTS Around a Byte FIFO 1200 Implement Medium Browser

Module P7 · Protocols · P7 SPI and QSPI

  1. P7.1.1 An Eight-Clock SPI Peripheral 825 Implement Easy Browser
  2. P7.4.2 Load Three Devices Through One Chain 1200 Implement Medium Browser
  3. P7.5.1 A Monitor for All Four SPI Modes 1200 Implement Medium Browser
  4. P7.6.1 Decode the Flash Read Phases 1200 Implement Medium Browser
  5. P7.8.1 WEL and BUSY at a Flash Command Boundary 1200 Implement Medium Browser
  6. P7.9.1 Fetch a Wrapped Quad Flash Line 1650 Implement Hard Simulation + synthesis

Module P8 · Protocols · P8 I2C

  1. P8.1.1 Read the Open-Drain Driver View 825 Implement Easy Browser
  2. P8.2.1 Recognize START STOP and Repeated START 825 Implement Easy Simulation + synthesis
  3. P8.3.1 Receive Eight Bits and Own the Ninth 825 Implement Easy Browser
  4. P8.4.1 A Register Target with Repeated START 1650 Implement Hard Browser
  5. P8.6.3 A Controller That Withdraws on Arbitration Loss 1650 Implement Hard Browser
  6. P8.8.1 Recover a Stuck SDA with at Most Nine Clocks 1650 Implement Hard Browser
  7. P8.10.1 Decode Seven-Bit Ten-Bit and General-Call Traffic 1650 Implement Hard Browser
  8. P8.13.1 Budget the Clock from Measured Bus Edges 825 Implement Easy Browser
03

High-Speed Interface Protocols

The links that carry data off the chip at speed.

Coming soon