Start Anywhere. Go All the Way.

New to Chip Design

See what your code becomes in gates, then follow it all the way to a layout.

1. R1.1What Synthesis Does with Your Code20 min
2. R1.2The Design Brief25 min
3. R1.3always_comb and the Latch Nobody Asked For25 min
4. R2.1always_ff, Old State and Next State25 min
5. L1.1What the Flow Does and Why25 min

Moving from RTL to Verification

You already write the design. Now learn to prove it and to break it on purpose.

1. 1.1Four-State vs Two-State Types20 min
2. 6.1Interfaces and Modports20 min
3. A1.1Why Assertions20 min
4. C1What Coverage Measures20 min
5. U1.1From a Layered Bench to UVM25 min

Interview Prep: Problems by Difficulty

Warm up on easy blocks, then climb to the asynchronous FIFO. A real simulator grades each one.

• Easy95
• Medium200
• Hard116
• Expert2

1. 1.1.1Unknown-Bit CounterEasy
2. R1.1.1A Four-Input MuxEasy
3. R4.4.1A Skid BufferMedium
4. R5.4.1A Round Robin for Any NMedium
5. R6.6.1The Asynchronous FIFOExpert

Learn Bus Protocols

Handshakes and bursts first, then the AMBA buses: AXI, APB and AHB.

1. P1.1Why a Bus Needs Rules25 min
2. P1.3Handshakes: Request and Acknowledge, Valid and Ready30 min
3. P2.1AXI in One Picture30 min
4. P3.1APB in One Picture25 min
5. P4.1AHB in One Picture25 min