ASIC Point Explore

Silicon Lab

Formal Verification Problems

Build a design, hunt its bugs, or repair what fails. Every answer runs on a real simulator.

Build starts from a specification: make it work, then make it small or fast. Bug Hunt asks for the checker or the test that catches broken designs. Repair hands you a failure: find the cause, then fix the design.

Formal Verification · F1

  1. F1.4.1 The Acknowledgement After Cancellation 900 Debug Easy Verilator
  2. F1.4.2 A Failure Before the First Request 900 Debug Easy Verilator

Formal Verification · F2

  1. F2.4.2 A Counterexample to Which Question? 1200 Debug Medium Verilator
  2. F2.6.1 Read the Timeout Without Inventing a Bug 1200 Debug Medium Verilator

Formal Verification · F3

  1. F3.3.1 Four Traces, Four Causes 1500 Debug Hard Verilator
  2. F3.5.2 The Overflow That Cannot Be Reached 1200 Debug Medium Verilator

Formal Verification · F4

  1. F4.2.2 The Cut That Removed the Bug 1200 Debug Medium Verilator

Formal Verification · F5

  1. F5.3.2 The Swapped Pair in the Table 1200 Debug Medium Verilator
  2. F5.9.1 Read the Lab Constraint Experiment 1200 Debug Medium Verilator

Formal Verification · F6

  1. F6.5.2 Explain the Surviving Mutation 1200 Debug Medium Verilator

Formal Verification · F7

  1. F7.5.1 Review the Missing Depth Argument 1200 Debug Medium Verilator

Formal Verification · F8

  1. F8.4.1 Locate the Circular Handshake Wait 1200 Debug Medium Verilator

Formal Verification · F9

  1. F9.4.1 Five Traces at the Interview 1500 Debug Hard Verilator