ASIC Point Explore

Silicon Lab

Formal Verification Problems

Build a design, hunt its bugs, or repair what fails. Every answer runs on a real simulator.

Build starts from a specification: make it work, then make it small or fast. Bug Hunt asks for the checker or the test that catches broken designs. Repair hands you a failure: find the cause, then fix the design.

Formal Verification · F2

  1. F2.1.1 Write the Third Toggle Stage 900 Implement Easy Verilator

Formal Verification · F3

  1. F3.1.1 Build the Register-Slice Checker 1200 Implement Medium Verilator
  2. F3.5.1 Ask for Three Directed Tests 1200 Implement Medium Verilator

Formal Verification · F4

  1. F4.3.1 An Exhaustive Address Case Split 1200 Implement Medium Verilator
  2. F4.4.1 Implement the Symbolic Packet Tracker 1500 Implement Hard Verilator
  3. F4.6.2 Conserve the Credits 1200 Implement Medium Verilator

Formal Verification · F5

  1. F5.3.1 Turn the Connection Table into Claims 1200 Implement Medium Verilator
  2. F5.8.1 Compare All Forbidden Sinks 1500 Implement Hard Verilator

Formal Verification · F6

  1. F6.5.1 Kill the Data-Path Survivors 1500 Implement Hard Verilator

Formal Verification · F7

  1. F7.1.1 Map the Registers Each Property Can See 1200 Implement Medium Verilator

Formal Verification · F8

  1. F8.3.1 Implement a Sound Expiry Abstraction 1500 Implement Hard Verilator
  2. F8.7.1 Check the Retired Register Value 1500 Implement Hard Verilator

Formal Verification · F9

  1. F9.2.2 Build the Router Packet Tracker 1500 Implement Hard Verilator