Silicon Lab
Formal Verification Problems
Build a design, hunt its bugs, or repair what fails. Every answer runs on a real simulator.
Optimize Problems
Build starts from a specification: make it work, then make it small or fast. Bug Hunt asks for the checker or the test that catches broken designs. Repair hands you a failure: find the cause, then fix the design.
Branches follow problem ratings. Choose any available problem.
- Easy
- Medium
- Hard
- Expert
- Solved
- Started
- Your next challenges
- Sign in to open
- Draft
Sign in to earn a rating and open every challenge.
Formal Verification · F2
- F2.4.1 Close the Induction with a Helper Optimize Hard Verilator
- F2.5.1 Let the Engine Find the Invariant Optimize Medium Verilator
Formal Verification · F4
- F4.1.1 Cut the Watchdog Cone Optimize Hard Verilator
- F4.2.1 A Free CRC Cut Optimize Hard Verilator
- F4.5.2 Qualify a Smaller Parameter Instance Optimize Medium Verilator
- F4.5.1 Abstract the Million-Cycle Watchdog Optimize Hard Verilator
- F4.6.1 Two Relations for Two Enables Optimize Hard Verilator
Formal Verification · F6
- F6.3.1 Partition the Multiplier Question Optimize Hard Verilator
Formal Verification · F8
- F8.1.2 Strengthen the FIFO Induction Optimize Hard Verilator
No problems in this format yet.