ASIC Point

OpenROAD · SKY130

Physical Design

Constrain timing, place cells, build a clock tree and route a SKY130 block with OpenROAD.

Eight modules, from standard cells to complete blocks.

Try RTL → GDSII
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Measured in OpenROAD · 8-bit MAC · SKY130Explore this layout

Explore the Lessons

Open a module to see its lessons.

How does a netlist become a chip?

Physical Design

Take a netlist to a placed and routed block: standard cells and the library, static timing analysis from the Liberty tables to the SDC, floorplan, placement, clock tree and routing, each step run with OpenROAD on the page.

47 lessons
  1. L1

    From Netlist to Layout

    6 lessons

    Name every stage of the physical design flow and the files it reads and writes, read a standard cell in its LEF and Liberty views, and measure a design in area, rows and sites.

    1. L1.1What the flow does and why
    2. L1.2Standard cells: the library's building blocks
    3. L1.3Your RTL in real cells
    4. L1.4The files of a physical design flow
    5. L1.5Rows, sites, tracks and the metal stack
    6. L1.6Reading a flow log
  2. L2

    Static Timing Analysis

    9 lessons

    Compute a cell delay from the Liberty tables and match the tool, follow arrival times and slews along a path, write the setup and hold checks with skew and uncertainty, and constrain a block with SDC.

    1. L2.1Timing arcs: what a cell promises
    2. L2.2Delay and slew from the Liberty tables
    3. L2.3The timing graph: arrival times and slew
    4. L2.4Setup and hold with skew and uncertainty
    5. L2.5Reading a timing report
    6. L2.6Clocks in SDC
    7. L2.7Input and output delays
    8. L2.8False paths and multicycle paths
    9. L2.9Corners, derates, OCV and CPPR
  3. L3

    Floorplan and Power

    5 lessons

    Turn a cell area into a core with a chosen utilization and aspect ratio, place I/O pins on purpose, leave room around macros, build the power grid layer by layer with its well taps, and measure static IR drop.

    1. L3.1Die, core, utilization and aspect ratio
    2. L3.2Pin placement
    3. L3.3Macros, halos and channels
    4. L3.4The power grid and well taps
    5. L3.5IR drop and electromigration
  4. L4

    Placement

    5 lessons

    Compute HPWL and read the placer's overflow log, choose a target density and find a congestion hotspot, check a legal placement and its displacement, repair slew, capacitance and fanout, and win back the slack the first wire delays take.

    1. L4.1Global placement and wirelength
    2. L4.2Density and congestion
    3. L4.3Legalization and detailed placement
    4. L4.4Repairing design rules: slew, capacitance, fanout
    5. L4.5Timing-driven placement and the first wire delays
  5. L5

    Clock Tree Synthesis

    6 lessons

    Tell global skew from the local skew that enters a slack, build the MAC's clock tree and read its buffers, insertion delay, skew and power, budget I/O paths for the moment the clock becomes propagated, borrow time with useful skew, repair hold after CTS, and choose where a clock-gating cell sits in the tree.

    1. L5.1Skew, latency and insertion delay
    2. L5.2Building the tree
    3. L5.3From ideal to propagated clocks
    4. L5.4Useful skew: borrowing time between stages
    5. L5.5Hold repair after CTS
    6. L5.6Clock gating cells in the tree
  6. L6

    Routing

    6 lessons

    Plan routes, resolve geometric constraints, extract wire parasitics, and check coupling and manufacturing antennas.

    1. L6.1Global routing: the plan for every net
    2. L6.2Detailed routing: tracks, vias and design rules
    3. L6.3Congestion and detours
    4. L6.4Wire RC and parasitic extraction
    5. L6.5Crosstalk and signal integrity
    6. L6.6Antenna rules
  7. L7

    Sign-Off

    6 lessons

    Audit final timing, geometry, connectivity, fill and controlled design changes.

    1. L7.1Sign-off timing: every corner, every check
    2. L7.2DRC: check the final shapes
    3. L7.3LVS: compare the extracted circuit
    4. L7.4Fill: cells, metal and density
    5. L7.5ECO: measure every change
    6. L7.6The sign-off review
  8. L8

    Physical Design Capstones

    4 lessons

    Constrain, diagnose, compare and document four complete physical-design jobs.

    1. L8.1Capstone: constrain the asynchronous FIFO
    2. L8.2Capstone: diagnose hold after CTS
    3. L8.3Capstone: a register file in a fixed die
    4. L8.4Capstone: RTL to a reviewed physical handoff