ASIC Point Explore

Silicon Lab

Formal Verification Problems

Build a design, hunt its bugs, or repair what fails. Every answer runs on a real simulator.

Build starts from a specification: make it work, then make it small or fast. Bug Hunt asks for the checker or the test that catches broken designs. Repair hands you a failure: find the cause, then fix the design.

Formal Verification · F1

  1. F1.2.1 Retire the Response, Including Errors 1200 Verify Medium Verilator
  2. F1.5.1 How Deep Is the Expiry Corner? 1200 Verify Medium Verilator

Formal Verification · F2

  1. F2.3.1 Three Bytes Before the Bad State 1200 Verify Medium Verilator

Formal Verification · F3

  1. F3.1.2 Check the Transformed Payload 1200 Verify Medium Verilator
  2. F3.3.2 One Promise for Speculative Capture 1500 Verify Hard Verilator
  3. F3.4.1 Prove the Data, Not Just the Pointers 1500 Verify Hard Verilator

Formal Verification · F4

  1. F4.4.2 Identity Before Payload Equality 1500 Verify Hard Verilator

Formal Verification · F5

  1. F5.2.1 Generate the Automatic Safety Checks 1200 Verify Medium Verilator
  2. F5.4.1 Check the Register Policy Table 1500 Verify Hard Verilator
  3. F5.5.2 Keep an Unknown from Enabling the Block 1200 Verify Medium Verilator
  4. F5.6.1 Check a Scheduled Clock Crossing 1500 Verify Hard Verilator
  5. F5.7.1 Prove the Dead Bins and Reach the Live One 1200 Verify Medium Verilator

Formal Verification · F6

  1. F6.1.1 Compare RTL with a Structural Implementation 1200 Verify Medium Verilator
  2. F6.2.1 Align a Two-Stage Adder 1500 Verify Hard Verilator
  3. F6.4.1 Constrain the Scope of a WRAP Fix 1500 Verify Hard Verilator

Formal Verification · F7

  1. F7.2.1 Close the FIFO Coverage Argument 1500 Verify Hard Verilator

Formal Verification · F8

  1. F8.1.1 Sign off a Four-Entry FIFO 1500 Verify Hard Verilator
  2. F8.5.1 One APB Contract on Both Sides 1500 Verify Hard Verilator
  3. F8.6.1 Forward the Newest Buffered Write 1500 Verify Hard Verilator

Formal Verification · F9

  1. F9.1.1 Sign off the AXI4-Lite Register Block 1500 Verify Hard Verilator
  2. F9.2.1 Prove Packet Routing End to End 1500 Verify Hard Verilator