Receive one mode-0 byte while returning a reply byte on the same eight clocks.
Hardware context: SPI peripherals and a quad flash command controller. Respect mode-dependent sample edges, command phases, storage boundaries and turnaround.
Receive one mode-0 byte while returning a reply byte on the same eight clocks.
Signals in the Timeline
| Signal | Width | Role |
|---|---|---|
cs_n | 1 | stimulus, the same for every design |
sclk | 1 | stimulus, the same for every design |
mosi | 1 | stimulus, the same for every design |
miso | 1 | stimulus, the same for every design |
oe | 1 | stimulus, the same for every design |
Full specification
On CS falling, clear the bit count and complete, and preload reply[7]. Sample MOSI on rising SCLK while selected; change MISO on falling SCLK.
After eight samples, publish received and assert complete. Further complete bytes may follow under the same CS. A new CS resets framing; an incomplete byte must not publish received.
oe is high exactly while selected. Use a 0/1/z MISO assignment; the driver-enable is the portable ownership observation.
Examples
Example 1
Full Duplex Byte- Input
MOSI 0x96, reply 0xa6, 8 clocks
- Output
received_mosi = 0x96, returned_miso = 0xa6, complete = yes, deselected_oe = no
Eight rising edges assemble MOSI in order. The reply was already available before each sample; CS release removes the MISO driver.
Example 2
A Different Reply- Input
MOSI 0x55, reply 0x3c, 8 clocks
- Output
received_mosi = 0x55, returned_miso = 0x3c, complete = yes, deselected_oe = no
Eight rising edges assemble MOSI in order. The reply was already available before each sample; CS release removes the MISO driver.
Example 3
Abort Before a Byte- Input
MOSI 0xff, reply 0x0, 3 clocks
- Output
received_mosi = 0x0, returned_miso = 0x0, complete = no, deselected_oe = no
A partial frame is discarded. No received byte is published, and the MISO driver releases with CS.
Constraints and Contract
- Implement spi_shift. The controller owns sclk, mosi and active-low cs_n. The peripheral drives MISO only while selected, with MSB first and mode-0 rising-edge sampling.
Hints
Hint 1
Write down which device owns each wire at the observation edge.
Hint 2
Separate framing and data state; decide what a new frame resets.
Hint 3
Check the shortest legal transfer and the boundary where a counter wraps.
What the grader checks: The fixture drives real pins through the shared serial library. Results check the specified digital contract. Electrical rise time, analog noise and hardware CDC signoff are outside this simulation.
5 checks on Icarus Verilog · browser. Run the examples first, then check the full regression. The suite is local and inspectable. A passing result establishes the tested cases, not a proof for all possible inputs.
See all 1 steps and the final capstone