Automatic Bins on an 8-Bit Value

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItCompareScale It

1. Automatic Bins on an 8-Bit Value
2. What IfAutomatic Bins on an EnumL1 Junior

   Asked if they mention enums

   What if the coverpoint is on an enum with three named values, and auto_bin_max is set to 2?

   module tb;
     typedef enum bit [3:0] {IDLE = 0, BUSY = 5, DONE = 9} st_t;
     st_t st;
     covergroup cg;
       cp: coverpoint st { option.auto_bin_max = 2; }
     endgroup
     cg c = new();
     initial begin
       st = IDLE; c.sample();
       st = BUSY; c.sample();
       $display("enum coverage=%0.2f", c.get_coverage());
     end
   endmodule
   

   Reveal the Model Answer

   An enum coverpoint gets one automatic bin per named value, and auto_bin_max does not apply. So there are three bins, and two samples give 66.67%. Values the enum type could hold but does not name get no bins.

   RUNVerilator (coverage build) · simulator service

   Edit the code, then run it

   OutputWaves

   RunReset codeExpected: enum coverage=66.67

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 An enum coverpoint gets one automatic bin per named value, and auto_bin_max does not apply. Key point 2 So there are three bins, and two samples give 66.67%. Key point 3 Values the enum type could hold but does not name get no bins.

   Misconception

   "auto_bin_max = 2 squeezes the enum into two bins."

   For an enum, the number of automatic bins is the number of named values. The run shows three bins.

   Source IEEE 1800-2017 §19.5.3

   • Lesson C2Covergroups and Coverpoints
3. CompareAutomatic vs Explicit BinsL1 JuniorL2 Mid-Level

   Compare automatic bins with bins you write yourself. When is each the right choice?

   Reveal the Model Answer

   Automatic bins are fine when there are few values and every one matters, such as an enum or a 3-bit field. Write explicit bins when the value is wide or when only some values matter. Explicit bins follow the spec: corners, ranges where the design behaves differently, and values that must never appear. They also give the report readable names.

   	Automatic bins	Explicit bins
   Good for	Few values that all matter: an enum, a 3-bit field	Wide values, or values where only some matter
   Bin edges come from	Arithmetic	The spec: ranges, edges, forbidden values
   Report names	auto[...]	Names you chose

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Automatic bins are fine when there are few values and every one matters, such as an enum or a 3-bit field. Key point 2 Write explicit bins when the value is wide or when only some values matter. Key point 3 Explicit bins follow the spec: corners, ranges where the design behaves differently, and values that must never appear. Key point 4 They also give the report readable names.

   What Interviewers Listen For (Mid-Level)

   A good mid-level answer links every explicit bin to a line in the spec or the plan. It also says which values were left out on purpose.

   Half-Truth

   "Automatic bins are safer because the tool cannot forget a value."

   The tool groups values without knowing the spec. A boundary such as 255 vs 256 can land inside one group and never be seen.

   Source Mehta, SystemVerilog Assertions and Functional Coverage (3rd ed.), §27.1 (PDF p502)

   • Lesson C3Choosing Bins
4. Scale ItAutomatic Bins on a 32-Bit AddressL2 Mid-Level

   A teammate puts a coverpoint with automatic bins on a 32-bit address and reports 100%. What does that number tell you?

   Reveal the Model Answer

   Almost nothing. With 64 automatic bins, each bin spans 2 to the power 26 addresses, about 67 million. One access anywhere in each slice covers it. The model says nothing about alignment, region boundaries or the last address of a region. Replace it with bins for the address map. Cover each region, its first and last word, and unaligned accesses if the bus allows them.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Almost nothing. Key point 2 With 64 automatic bins, each bin spans 2 to the power 26 addresses, about 67 million. Key point 3 One access anywhere in each slice covers it. Key point 4 The model says nothing about alignment, region boundaries or the last address of a region. Key point 5 Replace it with bins for the address map. Key point 6 Cover each region, its first and last word, and unaligned accesses if the bus allows them.

   Wrong Altitude

   "Raise auto_bin_max until the bins are small enough."

   More slices still ignore the address map. Region edges fall wherever the arithmetic puts them, and the model grows without becoming meaningful.

   Source Spear & Tumbush, SystemVerilog for Verification (3rd ed.), §9.10 (PDF p392)

   • Lesson C3Choosing Bins
   • Lesson C7Closing Holes
5. WhyWhy Automatic Bins Have a CapL1 Junior

   Why does the language cap automatic bins at all, instead of one bin per value?

   Reveal the Model Answer

   Without a cap, a 32-bit coverpoint would need over four billion bins. That costs memory, slows every sample and makes a report nobody can read. The cap keeps a forgotten coverpoint from exploding. You can change it per coverpoint or per covergroup with option.auto_bin_max.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Without a cap, a 32-bit coverpoint would need over four billion bins. Key point 2 That costs memory, slows every sample and makes a report nobody can read. Key point 3 The cap keeps a forgotten coverpoint from exploding. Key point 4 You can change it per coverpoint or per covergroup with option.auto_bin_max.

   Tool as Truth

   "The cap is a tool setting that differs between simulators."

   The cap and its default of 64 are in the standard's option table, so every compliant tool starts from the same number.

   Source Mehta, Introduction to SystemVerilog, Table 15.3 (PDF p614)

   • Lesson C3Choosing Bins
6. Prove ItSolve 7.5.8: Two Coverpoints for the FIFOSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem 7.5.8