Cover Property vs Covergroup

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfBreak ItCompareScale It

1. Cover Property vs Covergroup
2. CompareCover Sequence vs Cover PropertyL2 Mid-Level

   Compare cover sequence (req ##[1:3] gnt) with cover property (req ##[1:3] gnt). Can their counts differ?

   Reveal the Model Answer

   Yes. cover property counts at most one success per attempt. cover sequence counts every match, so one attempt can count several times. Suppose gnt is high in all three cycles after one req. The sequence cover counts three matches, and the property cover counts one. Use the property form to count scenarios, and the sequence form to see how often each ending happens.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Yes. Key point 2 cover property counts at most one success per attempt. Key point 3 cover sequence counts every match, so one attempt can count several times. Key point 4 Suppose gnt is high in all three cycles after one req. Key point 5 The sequence cover counts three matches, and the property cover counts one. Key point 6 Use the property form to count scenarios, and the sequence form to see how often each ending happens.

   Spec Misquote

   "They are two spellings of the same statement."

   The standard defines different counting: per attempt for properties, per match for sequences.

   Source IEEE 1800-2017 §16.14.3

   • Lesson A2.1Delays and Ranges: One Attempt, Many Threads
3. What IfTemporal Coverage in a Class-Based BenchL2 Mid-Level

   Asked if they work in a class-based bench

   What if your bench is all classes? Where does coverage of a timed sequence go?

   Reveal the Model Answer

   Put the cover property in the interface or in a checker bound to the design; classes cannot hold it. Or let the monitor turn the timing into a value, such as a stall length per transfer. Then sample that value in a covergroup. The covergroup route gives bins and crosses with other transaction fields. The interface route stays closest to the signals.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Put the cover property in the interface or in a checker bound to the design; classes cannot hold it. Key point 2 Or let the monitor turn the timing into a value, such as a stall length per transfer. Key point 3 Then sample that value in a covergroup. Key point 4 The covergroup route gives bins and crosses with other transaction fields. Key point 5 The interface route stays closest to the signals.

   Spec Misquote

   "Write cover property inside the monitor class."

   Concurrent assertions and covers are not allowed in classes. The compile fails.

   Source Mehta, SystemVerilog Assertions and Functional Coverage (3rd ed.), §25.3 (PDF p445)

   • Lesson A7.1Packaging and Binding
   • Lesson C6Coverage in a Class
4. WhySampling a Covergroup When a Sequence MatchesL2 Mid-LevelL3 Senior

   Can a sequence in the interface feed a covergroup directly, so a timed event gets bins and crosses?

   Reveal the Model Answer

   Yes. A sequence can call a function when it matches, for example (req ##[1:3] gnt, cg.sample(len)). With with function sample(...), the covergroup receives the values seen at that match, even local variables of the sequence. That gives a timed event, such as a grant latency, real bins and crosses.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Yes. Key point 2 A sequence can call a function when it matches, for example (req ##[1:3] gnt, cg.sample(len)). Key point 3 With with function sample(...), the covergroup receives the values seen at that match, even local variables of the sequence. Key point 4 That gives a timed event, such as a grant latency, real bins and crosses.

   Misconception

   "Assertions and covergroups can't talk to each other."

   Subroutine calls on a sequence match exist for exactly this. Passing the values as sample arguments keeps them correct for that match.

   Source Mehta, Introduction to SystemVerilog, §15.14 user-defined sample (PDF p613)

   • Lesson A4.1Remembering Data with Local Variables
   • Lesson C6Coverage in a Class
5. Scale ItWhat a Cover Means in FormalL2 Mid-LevelL3 Senior

   In formal verification, what does a cover property tell you that a simulation count cannot?

   Reveal the Model Answer

   Formal tries to reach the cover from reset under the assumptions. A reached cover comes with a trace, which proves the scenario can happen. An unreachable cover proves it cannot happen under those assumptions. That often means the assumptions are too tight, so covers are the main check against over-constraint.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Formal tries to reach the cover from reset under the assumptions. Key point 2 A reached cover comes with a trace, which proves the scenario can happen. Key point 3 An unreachable cover proves it cannot happen under those assumptions. Key point 4 That often means the assumptions are too tight, so covers are the main check against over-constraint.

   What Interviewers Listen For (Senior)

   A good senior answer writes covers for the key scenarios before trusting any proof. It treats an unreachable cover as a finding to investigate.

   Half-Truth

   "A cover that formal cannot reach is a design bug."

   It may be an over-constrained assumption, or a scenario the spec really forbids. Check the assumptions before blaming the design.

   Source Seligman, Schubert, Kiran Kumar, Formal Verification (2nd ed.), ch. 9, an over-tight assumption (PDF p312)

   • Lesson F1.3Assert, Assume, Cover: The Three Verbs
   • Lesson F7.2Property Completeness
6. Break ItA Cover Reached During ResetL2 Mid-Level

   How could a cover property report a hit that never happened in real traffic?

   Reveal the Model Answer

   If the sequence can match on reset values, it is covered while the design is held in reset. For example, !valid ##1 !valid matches on any two reset cycles. Add disable iff (rst) to the cover, or include a real event such as valid && ready in the sequence.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 If the sequence can match on reset values, it is covered while the design is held in reset. Key point 2 For example, !valid ##1 !valid matches on any two reset cycles. Key point 3 Add disable iff (rst) to the cover, or include a real event such as valid && ready in the sequence.

   Missed Corner

   "Covers don't need reset handling; only assertions do."

   Reset values are as real to a cover as to an assertion. Without disable iff, reset cycles can satisfy it.

   Source Seligman, Schubert, Kiran Kumar, Formal Verification (2nd ed.), ch. 9, misleading cover with bad reset (PDF p310)

   • Lesson A3.5Reset and Abort: disable iff, Accept and Reject