← Design Verification Interviews
Interview Question · Code Writing
Keeping Reset Out of Coverage
The Question
The interviewer asks
A clocked covergroup covers a FIFO's fill level, with bins for empty, partial and full. Write it so that reset cycles cannot cover any bin.
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Reveal the Model Answer
Add a guard to the coverpoint: coverpoint level iff (!rst). During reset the design holds known values, such as a level of 0, and a clocked covergroup counts them. The empty bin is then covered by reset alone, even if the FIFO never drains in the test. With the guard false, the coverpoint ignores that sample.
One column per rising edge. The FIFO never drains to empty after reset, and only the guarded coverpoint shows it.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer writes the iff (!rst) guard. It also says which bin reset would fill without it: the empty bin.
What Interviewers Listen For (Mid-Level)
A good mid-level answer also covers reset as a case of its own, such as a reset while the FIFO is full. It does not only exclude reset.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfCompareScale It
- Keeping Reset Out of Coverage
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CompareIff Guards vs Stop and StartL1 JuniorL2 Mid-Level
Compare the
iffguard with callingcg.stop()during reset andcg.start()after it.2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
The guard is part of the coverage model and works the same in every test.
stop()andstart()are calls the test must remember to make, so a test that forgets them counts reset again. They are useful for switching a whole group off in a phase of the test. Check your tool before relying on them; this site's coverage build ignoresstop().iffguardstop()andstart()Part of The coverage model The test Works in every test Yes Only if the test makes the calls Scope One coverpoint A whole covergroup instance On the coverage build of this site Works stop()is ignoredA guard travels with the covergroup. The calls depend on every test remembering them.
Self-Check
Tick each key point you covered in your answer.
Tool as Truth
"
stop()is safe everywhere because it is in the standard."The standard defines it, but tools differ. The twin calls
stop()and the samples taken while stopped still count on this site's build.Run It
Two samples while stopped, one after start.
RUNVerilator (coverage build) · simulator serviceExpected:coverage=75.00 (the standard says 25.00: only the sample after start counts)FAIL: this simulator ignored stop(), so samples taken while stopped were counted -
What IfCovering a Reset in the Middle of TrafficL2 Mid-Level
Asked if they mention a reset in the middle of a test
What if the spec allows a reset in the middle of traffic? Is excluding reset still the right model?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
No, a mid-test reset is a feature to cover, not noise. Keep the
iff (!rst)guard on the normal coverpoints, and add a coverpoint sampled at the rising edge of reset. Its bins say what the design was doing when reset arrived: empty, partial, full, or in the middle of a transfer. Each bin is a recovery case the bench must check.Self-Check
Tick each key point you covered in your answer.
Missed Corner
"Reset is tested once at time zero, so it is covered."
Power-on reset starts from an empty design. Reset with data in flight tests the recovery logic, which time-zero reset never touches.
Source Mehta, SystemVerilog Assertions and Functional Coverage (3rd ed.), §25.5 (PDF p447)
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Scale ItReset Coverage Across a ChipL3 Senior
At chip level there are several reset sources and domains. Which reset scenarios go into the coverage plan?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
List each reset source and what it resets: power-on, warm reset, watchdog, and per-domain or per-block resets. Cover each one while traffic is in flight, and cover one domain resetting while its neighbours keep running. Cross the reset with the state of the bus between the domains. Those crossings are where hangs and lost transactions appear.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Senior)
A good senior answer builds the plan from the chip's reset architecture document. It names a reset that crosses between domains as the highest risk.
Wrong Altitude
"Each block covered its own reset, so the chip is covered."
Block benches reset everything at once. Partial resets between running blocks exist only at chip level.
Source Spear & Tumbush, SystemVerilog for Verification (3rd ed.), §9.2.2 (PDF p364)
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WhyWhy Guard Each CoverpointL1 Junior
Why put
iffon each coverpoint instead of wrapping the wholesample()call inif (!rst)?2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
A per-coverpoint guard lets one covergroup mix rules. Normal coverpoints ignore reset, while a reset coverpoint in the same group samples only during reset. Wrapping the call is fine when every coverpoint shares one rule. With a clocked covergroup there is no call to wrap, so the guard is the only option.
Self-Check
Tick each key point you covered in your answer.
Half-Truth
"The two are identical in every case."
They match only when all coverpoints share the condition. A wrapped call also stops the coverpoints that should count during reset.
Source IEEE 1800-2017 §19.5
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Missed Corner
"Reset cycles do no harm; they are only a few samples."
One sample is enough to cover a bin. In the twin the FIFO never drains to empty, and the reset cycles cover the empty bin anyway.
Run It
A FIFO that fills and drains to 1, never to empty.
level coverage=100.00 FAIL: the empty bin was covered only by reset cycles; the FIFO never drained to emptySee the Fix
module tb;
logic clk = 0;
always #5 clk = ~clk;
logic rst = 1;
int level = 0; // FIFO fill level; reset holds it at 0
covergroup cg @(posedge clk);
cp: coverpoint level iff (!rst) { bins empty = {0}; bins partial = {[1:3]}; bins full = {4}; } // the fix: ignore reset cycles
endgroup
cg c = new();
int after_reset[$] = '{1, 2, 3, 4, 3, 2, 1}; // fills, then drains to 1, never to empty
initial begin
repeat (2) @(negedge clk);
foreach (after_reset[i]) @(negedge clk) begin rst = 0; level = after_reset[i]; end
@(negedge clk);
$display("level coverage=%0.2f", c.get_coverage());
if (c.get_coverage() == 100.0) $display("FAIL: the empty bin was covered only by reset cycles; the FIFO never drained to empty");
else $display("PASS: with iff (!rst) the report shows the FIFO never drained to empty");
$finish;
end
endmodule
Prints: level coverage=66.67 PASS: with iff (!rst) the report shows the FIFO never drained to empty
Misconception
"Use disable iff (rst) on the covergroup, like an assertion."
disable iff belongs to properties. A coverpoint or cross takes an iff guard instead.
Source IEEE 1800-2017 §19.5