Covering a Stall with Transition Bins

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WhyBreak ItCompareScale It

1. Covering a Stall with Transition Bins
2. WhyWhy Reduce the Handshake to One StateL1 Junior

   Why convert valid and ready into one state before writing transitions? Why not cross them?

   Reveal the Model Answer

   A transition bin follows one coverpoint's value from one sample to the next. A cross only pairs values within the same sample and has no memory of earlier ones. So valid crossed with ready shows that a stalled cycle happened, but not how long the stall lasted. One state per clock gives the transition something to follow.

   Every state value appears early. Only the order of the samples decides which transition bins fill.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 A transition bin follows one coverpoint's value from one sample to the next. Key point 2 A cross only pairs values within the same sample and has no memory of earlier ones. Key point 3 So valid crossed with ready shows that a stalled cycle happened, but not how long the stall lasted. Key point 4 One state per clock gives the transition something to follow.

   Half-Truth

   "A cross of valid and ready already shows the stall."

   It shows the stalled combination appeared at least once. It cannot tell a one-cycle stall from a five-cycle one.

   Source IEEE 1800-2017 §19.6

   • Lesson C4Transitions
   • Lesson C5Cross Coverage
3. CompareTransition Bins vs a Stall-Length CounterL2 Mid-Level

   Compare transition bins with a counter of stall cycles, sampled at each transfer. What does this print?

   module tb;
     logic clk = 0;
     always #5 clk = ~clk;
     bit valid, ready;
     int stall_len = 0;
     covergroup cg with function sample(int n);
       len: coverpoint n { bins none = {0}; bins one = {1}; bins two = {2}; bins long_ = {[3:16]}; }
     endgroup
     cg c = new();
     // valid/ready per clock: stalls of 0, 1 and 5 cycles.
     bit [1:0] vr[$] = '{2'b11, 2'b10, 2'b11, 2'b10, 2'b10, 2'b10, 2'b10, 2'b10, 2'b11, 2'b00};
     initial begin
       foreach (vr[i]) begin
         {valid, ready} = vr[i];
         @(posedge clk);
         if (valid && !ready) stall_len++;
         if (valid && ready) begin c.sample(stall_len); $display("transfer after %0d stall cycles", stall_len); stall_len = 0; end
       end
       $display("stall-length coverage=%0.2f", c.get_coverage());
       $finish;
     end
   endmodule
   

   Reveal the Model Answer

   It prints three transfers, after 0, 1 and 5 stall cycles, then 75% coverage, because no two-cycle stall happened. A counter handles any stall length with one coverpoint, and a range bin like [3:16] covers long stalls. Transition bins grow one bin per length and get unreadable past three or four cycles. Use transitions for short, exact patterns and a counter for lengths.

   RUNVerilator (coverage build) · simulator service

   Edit the code, then run it

   OutputWaves

   RunReset codeExpected: transfer after 0 stall cycles transfer after 1 stall cycles transfer after 5 stall cycles stall-length coverage=75.00

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 It prints three transfers, after 0, 1 and 5 stall cycles, then 75% coverage, because no two-cycle stall happened. Key point 2 A counter handles any stall length with one coverpoint, and a range bin like [3:16] covers long stalls. Key point 3 Transition bins grow one bin per length and get unreadable past three or four cycles. Key point 4 Use transitions for short, exact patterns and a counter for lengths.

   Missed Corner

   "A counter needs no care; just sample it every clock."

   Sampled every clock it counts the stall growing, so a five-cycle stall also covers 1, 2, 3 and 4. Sample it once, at the transfer.

   Source Mehta, SystemVerilog Assertions and Functional Coverage (3rd ed.), §26.19 guidelines (PDF p476)

   • Lesson C4Transitions
4. Scale ItStall Coverage on Twelve PortsL2 Mid-LevelL3 Senior

   An interconnect has 12 ports with the same handshake. How do you cover stalls on all of them without 12 copies of the code?

   Reveal the Model Answer

   Write the covergroup once, in the interface or in a coverage class, and create one instance per port. Set option.per_instance = 1 so the report shows each port. Remember that the type total averages the instances. Eleven busy ports and one dead port still look like 92%, so review the per-port numbers, not just the total.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Write the covergroup once, in the interface or in a coverage class, and create one instance per port. Key point 2 Set option.per_instance = 1 so the report shows each port. Key point 3 Remember that the type total averages the instances. Key point 4 Eleven busy ports and one dead port still look like 92%, so review the per-port numbers, not just the total.

   What Interviewers Listen For (Senior)

   A good senior answer asks for a report per port before trusting a combined number. It also asks which ports carry real traffic.

   Missed Corner

   "One shared instance for all ports is simpler."

   A shared instance merges the ports. A port that never stalls is hidden by the others, which is the hole you wanted to find.

   Source Spear & Tumbush, SystemVerilog for Verification (3rd ed.), §9.10.1 (PDF p392)

   • Lesson C6Coverage in a Class
5. WhyWhy the Type Figure Is an AverageL2 Mid-Level

   Why does the type figure read 50% when the instances together hit every bin?

   Reveal the Model Answer

   With merging off, each instance is scored against its own bins, and the type is the weighted average of those scores. Port A scores 50 and port B scores 50, so the type is 50. The rule asks "how well was each instance covered", not "was each bin hit somewhere". One idle instance therefore pulls the type figure down.

   Figure	Bins hit	Score
   Instance A	b[0], b[1]	50%
   Instance B	b[2], b[3]	50%
   Type, default (average)	each instance scored on its own	50%
   Type, merge_instances = 1 (union)	all four, from either instance	100%

   The same samples as the root question. Only the rule for combining instances changes.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 With merging off, each instance is scored against its own bins, and the type is the weighted average of those scores. Key point 2 Port A scores 50 and port B scores 50, so the type is 50. Key point 3 The rule asks "how well was each instance covered", not "was each bin hit somewhere". Key point 4 One idle instance therefore pulls the type figure down.

   Tool as Truth

   "The average rule is a tool bug."

   It is the standard's default. Tools that show the union have merge_instances set, or show a merged database view.

   Source Mehta, Introduction to SystemVerilog, Table 15.2 (PDF p613)

   • Lesson C6Coverage in a Class
6. Break ItTransition Bins Sampled on the Wrong ClockL2 Mid-Level

   How could these transition bins still mislead you? Suppose the covergroup samples on a core clock twice as fast as the bus.

   Reveal the Model Answer

   Every bus cycle is sampled twice, so each state appears twice in a row. A one-cycle stall then looks like WAIT => WAIT, and it covers the two-cycle bin instead. Transition bins count samples, not bus cycles. Sample on the bus clock, or call sample() once per bus cycle.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Every bus cycle is sampled twice, so each state appears twice in a row. Key point 2 A one-cycle stall then looks like WAIT => WAIT, and it covers the two-cycle bin instead. Key point 3 Transition bins count samples, not bus cycles. Key point 4 Sample on the bus clock, or call sample() once per bus cycle.

   Misconception

   "Sampling more often only makes coverage more accurate."

   Transitions are counted between consecutive samples. Extra samples insert repeated states, which changes which sequences appear. The twin covers the wrong bin.

   Run It

   A one-cycle stall, sampled twice per bus cycle.

   RUNVerilator (coverage build) · simulator service

   Edit the code, then run it

   OutputWaves

   RunReset codeExpected: one_stall=0.00 two_stall=100.00 FAIL: two samples per bus cycle turned the one-cycle stall into a two-cycle one

   See the Fix

   module tb;
     typedef enum bit [1:0] {IDLE, WAIT, XFER} st_t;
     st_t st;
     st_t bus[$] = '{IDLE, WAIT, XFER, IDLE};   // one entry per bus cycle: a one-cycle stall
     covergroup one_cg;
       cp: coverpoint st { bins one_stall = (IDLE, XFER => WAIT => XFER); }
     endgroup
     covergroup two_cg;
       cp: coverpoint st { bins two_stall = (IDLE, XFER => WAIT => WAIT => XFER); }
     endgroup
     one_cg one = new();
     two_cg two = new();
     initial begin
       foreach (bus[i]) begin
         st = bus[i];
         repeat (1) begin one.sample(); two.sample(); end   // the fix: one sample per bus cycle
       end
       $display("one_stall=%0.2f two_stall=%0.2f", one.get_coverage(), two.get_coverage());
       if (two.get_coverage() > 0) $display("FAIL: two samples per bus cycle turned the one-cycle stall into a two-cycle one");
       else $display("PASS: one sample per bus cycle covers the one-cycle stall only");
     end
   endmodule
   

   Prints: one_stall=100.00 two_stall=0.00 PASS: one sample per bus cycle covers the one-cycle stall only

   • Lesson C2Covergroups and Coverpoints
   • Lesson C4Transitions