← Design Verification Interviews
Interview Question · Concept
When Not to Use DPI
The Question
The interviewer asks
When would you advise a team against DPI? Give concrete cases.
You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Avoid DPI for work SystemVerilog already does well: random stimulus, waiting for time, small checks and text formatting. C rand() ignores the SystemVerilog seed and random stability, so a failing seed may not reproduce. DPI also adds a second build and debug flow, and a C bug crashes the whole simulation. Use it when a trusted model already exists in C, C++ or Python, or the algorithm is heavy.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
Gives at least two concrete cases, including random numbers from C, and one case where DPI is the right call.
What Interviewers Listen For (Senior)
Weighs reuse of an independent model against a second toolchain, and names seed reproducibility as the deciding risk for stimulus.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfBreak ItCompare
- When Not to Use DPI
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WhyWhy C Random Numbers Break Seed ReplayL2 Mid-Level
Why does C
rand()break seed reproducibility, when the test always calls it in the same place?2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
C
rand()is one stream shared by every caller in the process. Its next value depends on how many calls came before, from any thread or any model. Add one call in another component, and every later value moves. SystemVerilog avoids this by giving each thread and object its own generator.Self-Check
Tick each key point you covered in your answer.
Half-Truth
"Call
srand(seed)once at time 0, and it is reproducible."It repeats only while the order of every call stays the same. Any change to the bench, even in an unrelated agent, shifts the stream.
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What IfA C Model That Needs Random NumbersL2 Mid-LevelL3 Senior
What if the C model genuinely needs random numbers, for example to model random arbitration?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Give each model its own generator, such as a
std::mt19937inside the model struct. Seed it from a value SystemVerilog passes at creation, taken with$urandom. Then the SystemVerilog seed controls the model, and each model has its own stream.Self-Check
Tick each key point you covered in your answer.
Misconception
"Seed it from the time of day, so every run is different."
Then a failing run can never be repeated. Variety should come from changing the SystemVerilog seed on purpose.
Source IEEE 1800-2017 §18.14
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CompareDPI Compared with Precomputed Vector FilesL2 Mid-Level
Compare calling a model through DPI with running the model offline and reading its expected results from a file.
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Reveal the Model Answer
A vector file is simple: no shared build, and the model runs once. But the stimulus is fixed in advance, so the test cannot react to random choices, backpressure or resets. DPI keeps the model in the loop for every transaction. Use files for fixed directed suites, and DPI for constrained-random benches.
Self-Check
Tick each key point you covered in your answer.
Half-Truth
"Files are always safer, because there is no C in the simulation."
The file must match the stimulus exactly. Any change in random choices or timing makes the expected values wrong.
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Break ItA C++ Exception Thrown Through DPIL2 Mid-Level
Break it: the C++ model throws
std::out_of_rangeon a bad address, and nothing catches it. What happens?2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
The exception tries to unwind through simulator code that does not expect it. The standard calls that undefined behaviour. In practice the process usually stops in
std::terminatewith no test report. Wrap every import body intry/catchand return a status instead.Self-Check
Tick each key point you covered in your answer.
Misconception
"The simulator turns the exception into a SystemVerilog error."
DPI has no channel for exceptions. The only results are the return value and the output arguments.
Source IEEE 1800-2017 §35.5.1 (semantic constraints on imported routines)
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Misconception
"C rand() follows the SystemVerilog seed."
SystemVerilog gives each thread its own seeded generator. C rand() is one stream for the whole process, so equal seeds do not give equal values.
Run It
Two threads, both seeded with 42, each draw one SystemVerilog length and one C length.
SystemVerilog lengths: 42 and 42, C lengths: 39 and 6 FAIL: both threads had seed 42, but C rand() gave different lengths; it ignores SystemVerilog seedingSee the Fix
module tb;
import "DPI-C" function int c_len_from_seed(input int seed);
int sv_a, sv_b, c_a, c_b;
// Two threads with the same seed must make the same random choices.
initial begin
process::self().srandom(42);
sv_a = $urandom_range(63);
c_a = c_len_from_seed($urandom); // the fix: SystemVerilog supplies the seed
end
initial begin
#1;
process::self().srandom(42);
sv_b = $urandom_range(63);
c_b = c_len_from_seed($urandom);
$display("SystemVerilog lengths: %0d and %0d, C lengths: %0d and %0d", sv_a, sv_b, c_a, c_b);
if (c_a != c_b) $display("FAIL: both threads had seed 42, but C rand() gave different lengths; it ignores SystemVerilog seeding");
else $display("PASS: C drew from a seed SystemVerilog gave it, so equal seeds gave equal lengths");
$finish;
end
endmodule
Prints: SystemVerilog lengths: 42 and 42, C lengths: 23 and 23 PASS: C drew from a seed SystemVerilog gave it, so equal seeds gave equal lengths
Misconception
"Moving code into C always makes it faster."
For small work, SystemVerilog can win. Our probe ran the same CRC in 64 ms in SystemVerilog and in 120 ms through per-byte DPI.
Source Measured on a local Verilator 5.052 build with g++, 2026-11-08 (CRC in SystemVerilog against per-byte DPI, -O0)
Wrong Altitude
"Use DPI to read internal DUT signals from C."
C sees only its arguments. Probing belongs in SystemVerilog, through an interface, bind or a hierarchical reference, where the waveform shows it.
Delivery
Says only "avoid DPI, it is hard to debug", with no case where it is right.
A one-sided answer shows no judgement. The interviewer wants the trade-off, including when reuse of a C model wins.