Interview Question · Waveform

Input Skew of 1step vs Zero

L1 JuniorL2 Mid-Levelsystemverilogclocking blockssampling

The interviewer asks

A flop toggles at every rising edge. One clocking block samples it with input #1step, another with input #0. Read the waveform: what does each one record at each edge?

Reveal the Model Answer

#1step samples in the Preponed region, so it records the value the flop held before the edge: 0, 1, 0 at the three edges. #0 samples in the Observed region, after the flop's NBA update, so it records the new value: 1, 0, 1. A monitor almost always wants #1step, because that is the value a real flop on the same clock would capture.

One flop, two input skews

Each column is half a clock period. The flop changes at the rising edge; #1step records the value from just before it.

The Edge at t=5 Through a Clocking BlockOne rising edge through a clocking block with #1step input skew. The top row is the regions of the time step in order. The bottom row is the clockvar, the raw signal and the process waiting on @(bus.cb). Arrows show values moving, except the wake-up from Observed.

Sample firstt=5, Preponed (illustrative)
Before any process runs at t=5, rdata is 00. With #1step, that Preponed value is what bus.cb.rdata reports for this edge.
Follow the calls, values and waits
1. data rdata = 00: Preponed → bus.cb.rdata
The DUT reads the old valuet=5, Active (illustrative)
The DUT's always block runs in Active. Its <= reads 00, adds 11, and leaves the write for the NBA region.
Follow the calls, values and waits
1. data rdata <= 11: Active → NBA
The raw signal moves ont=5, NBA (illustrative)
The NBA region writes 11 to bus.rdata. From now on, a read of the raw signal gets the next beat.
Follow the calls, values and waits
1. data 11: NBA → bus.rdata
The clocking event firest=5, Observed (illustrative)
With the design settled, the clocking event is triggered in the Observed region. The process waiting on @(bus.cb) wakes, still at t=5.
Follow the calls, values and waits
1. call @(bus.cb): Observed → tb process
Two views of one signalt=5 (illustrative)
$display prints raw rdata=11, sampled bus.cb.rdata=00. Only the clockvar shows the pre-edge value, the one a flip-flop reading rdata captures at this edge.
Follow the calls, values and waits
1. data 00: bus.cb.rdata → tb process
2. data 11: bus.rdata → tb process

Read the diagram as text

Preponed: rdata is still 00
Active: DUT: rdata <= rdata + 11
NBA: the DUT update is written
Observed: the clocking event is triggered
bus.cb.rdata: clockvar: the #1step sample
bus.rdata: the raw signal
tb process: waits on @(bus.cb), then prints

Preponed → bus.cb.rdata: sample
Preponed → Active: then
Active → NBA: pending update
NBA → bus.rdata: write
NBA → Observed: design settled
Observed → tb process: wakes
bus.cb.rdata → tb process: reads cb.rdata
bus.rdata → tb process: reads rdata

The sample is fixed before the edge's updates, and the waiting process wakes after them. Reading the clockvar is what keeps the two in step.

The two clocking blocks, read 1 ns after each edge.

RUNVerilator · simulator service

Edit the code, then run it

Expected: t=6 #1step=0 #0=1 raw=1 t=16 #1step=1 #0=0 raw=0 t=26 #1step=0 #0=1 raw=1

module tb;
  logic clk = 0; always #5 clk = ~clk;      // rising edges at 5, 15, 25
  logic q = 0;
  always @(posedge clk) q <= ~q;            // the DUT flop toggles at every edge
  clocking cb_pre @(posedge clk); input #1step q; endclocking
  clocking cb_obs @(posedge clk); input #0 q; endclocking
  initial begin
    repeat (3) begin
      @(posedge clk); #1;
      $display("t=%0t  #1step=%0d  #0=%0d  raw=%0d", $time, cb_pre.q, cb_obs.q, q);
    end
    $finish;
  end
endmodule

Self-Check

Tick each key point you covered in your answer.

Key point 1 #1step samples in the Preponed region, so it records the value the flop held before the edge: 0, 1, 0 at the three edges. Key point 2 #0 samples in the Observed region, after the flop's NBA update, so it records the new value: 1, 0, 1. Key point 3 A monitor almost always wants #1step, because that is the value a real flop on the same clock would capture.

What Interviewers Listen For (Junior)

A good junior answer reads both rows off the waveform. It names the two regions where the samples are taken.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItCompareScale It

Input Skew of 1step vs Zero
CompareClocking Blocks vs Driving on the Falling EdgeL2 Mid-Level
Compare a clocking block with driving stimulus on the falling edge as ways to avoid testbench races.

Reveal the Model Answer

Driving on the falling edge puts drives and samples in different time steps, so it is simple and race-free. But it only works for single-edge designs with a known duty cycle. A clocking block samples inputs just before the active edge (#1step, the Preponed region). It drives outputs after a set skew, so the testbench stays cycle-based on the real edge. Clocking blocks scale to agents and interfaces; falling-edge drives suit small directed benches.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Driving on the falling edge puts drives and samples in different time steps, so it is simple and race-free. Key point 2 But it only works for single-edge designs with a known duty cycle. Key point 3 A clocking block samples inputs just before the active edge (#1step, the Preponed region). Key point 4 It drives outputs after a set skew, so the testbench stays cycle-based on the real edge. Key point 5 Clocking blocks scale to agents and interfaces; falling-edge drives suit small directed benches.

Spec Misquote

"An input skew of #1step means one nanosecond before the edge."

1step is one unit of the time precision, not one nanosecond. The sample is taken in the Preponed region, so it reads the values from just before the edge.

Source IEEE 1800-2017 §14.4, §4.4.2.1
- Lesson 6.3Clocking Blocks and Sampled Views
What IfReading a Clockvar After the Raw EdgeL2 Mid-Level
Asked if they write a monitor with clocking blocks

A monitor waits for @(posedge clk) and then reads cb.rdata. It sometimes reports the previous beat. What happened?
systemverilog
```
clocking cb @(posedge clk);
  default input #1step;
  input rdata;
endclocking
initial forever begin
  @(posedge clk);
  $display("rdata=%h", cb.rdata);
end
```
Reveal the Model Answer

Clockvars (the sampled signals of a clocking block) are updated when the clocking event is processed, in the Observed region. A process that resumes on the raw posedge clk can read cb.rdata before that update. It then gets the previous sample. Wait on @(cb) instead, so the read happens after the clockvars change.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Clockvars (the sampled signals of a clocking block) are updated when the clocking event is processed, in the Observed region. Key point 2 A process that resumes on the raw posedge clk can read cb.rdata before that update. Key point 3 It then gets the previous sample. Key point 4 Wait on @(cb) instead, so the read happens after the clockvars change.
- Lesson 6.3Clocking Blocks and Sampled Views
- Problem 6.3.1The Monitor That Read the Next Beat
What IfReading a Clockvar After the Raw EdgeL2 Mid-Level
Asked if their monitor waits on the raw clock

A monitor waits for @(posedge clk) and then reads cb.rdata. It sometimes reports the previous beat. What happened?
systemverilog
```
clocking cb @(posedge clk);
  default input #1step;
  input rdata;
endclocking
initial forever begin
  @(posedge clk);
  $display("rdata=%h", cb.rdata);
end
```
Reveal the Model Answer

Clockvars (the sampled signals of a clocking block) are updated when the clocking event is processed, in the Observed region. A process that resumes on the raw posedge clk can read cb.rdata before that update. It then gets the previous sample. Wait on @(cb) instead, so the read happens after the clockvars change.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Clockvars (the sampled signals of a clocking block) are updated when the clocking event is processed, in the Observed region. Key point 2 A process that resumes on the raw posedge clk can read cb.rdata before that update. Key point 3 It then gets the previous sample. Key point 4 Wait on @(cb) instead, so the read happens after the clockvars change.
- Lesson 6.3Clocking Blocks and Sampled Views
- Problem 6.3.1The Monitor That Read the Next Beat
WhyWhat an Output Skew DoesL1 JuniorL2 Mid-Level
Why do clocking blocks have an output skew, and when does a drive with output #2 reach the wire?
2:30

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Reveal the Model Answer

The output skew sets when a drive written to a clockvar appears on the signal, relative to the clocking event. With output #2, a drive requested at the edge at 5 reaches the wire at 7. That is well clear of the edge, so the DUT samples it at the next edge. It also models a real launch delay when a model needs one.

RUNVerilator · simulator service

Edit the code, then run it

Expected: t=7 d -> 1

Self-Check
Tick each key point you covered in your answer.
Key point 1 The output skew sets when a drive written to a clockvar appears on the signal, relative to the clocking event. Key point 2 With output #2, a drive requested at the edge at 5 reaches the wire at 7. Key point 3 That is well clear of the edge, so the DUT samples it at the next edge. Key point 4 It also models a real launch delay when a model needs one.
Misconception

"A clockvar drive changes the signal at once."

Clockvar drives are synchronous: they take effect at the output skew after the clocking event, as the run shows at t=7.

Source IEEE 1800-2017 §14.16
- Lesson 6.3Clocking Blocks and Sampled Views
Scale ItClocking Skews When the Design Has Real DelaysL3 Senior
The same bench now runs against a gate-level netlist with SDF delays. What changes in your clocking blocks?

Reveal the Model Answer

With real clock-to-output delays, outputs change some time after the edge. A #1step input still reads the old value safely. But a monitor must allow for the new value arriving later in the cycle. You can set input skews to match the hold window you want to check. Output skews must respect the DUT's setup and hold times, so the bench does not cause violations itself.

Self-Check
Tick each key point you covered in your answer.
Key point 1 With real clock-to-output delays, outputs change some time after the edge. Key point 2 A #1step input still reads the old value safely. Key point 3 But a monitor must allow for the new value arriving later in the cycle. Key point 4 You can set input skews to match the hold window you want to check. Key point 5 Output skews must respect the DUT's setup and hold times, so the bench does not cause violations itself.

What Interviewers Listen For (Senior)
A good senior answer links skews to setup and hold times at the boundary. It keeps one bench, with parameters, for both RTL and gate-level runs.

Half-Truth

"Skews only matter at gate level; in RTL they are cosmetic."

In RTL the skews decide which region samples and drives happen in, which is what removes TB-to-DUT races. At gate level they also carry real timing.

Source IEEE 1800-2017 §14.4
- Lesson 6.3Clocking Blocks and Sampled Views
Prove ItSolve 6.3.1: The Monitor That Read the Next BeatSimulator-graded

Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
Open Problem 6.3.1

What People Get Wrong

Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.

Misconception

"#0 and #1step sample the same value; both are at the edge."

They sample on opposite sides of the NBA update. In the twin a #0 monitor records the flop's next value instead of the one presented before the edge.

Run It

A monitor that should record the value presented before the edge at t=5.

RUNVerilator · simulator service

Edit the code, then run it

Expected: monitor recorded 11 FAIL: input #0 sampled in the Observed region, after the flop had already changed

module tb;
  logic clk = 0; always #5 clk = ~clk;
  logic [7:0] q = 8'h00;
  always @(posedge clk) q <= q + 8'h11;     // DUT output: 00, 11, 22, ...
  // The monitor should record the value the DUT presented before each edge.
  clocking cb @(posedge clk); input #0 q; endclocking   // the belief: #0 and #1step sample the same value
  initial begin
    @(cb);                                  // edge at 5: the DUT held 00 before it
    $display("monitor recorded %h", cb.q);
    if (cb.q !== 8'h00) $display("FAIL: input #0 sampled in the Observed region, after the flop had already changed");
    else $display("PASS: #1step recorded the value from before the edge");
    $finish;
  end
endmodule

See the Fix

module tb;
  logic clk = 0; always #5 clk = ~clk;
  logic [7:0] q = 8'h00;
  always @(posedge clk) q <= q + 8'h11;     // DUT output: 00, 11, 22, ...
  // The monitor should record the value the DUT presented before each edge.
  clocking cb @(posedge clk); input #1step q; endclocking   // the fix: sample just before the edge
  initial begin
    @(cb);                                  // edge at 5: the DUT held 00 before it
    $display("monitor recorded %h", cb.q);
    if (cb.q !== 8'h00) $display("FAIL: input #0 sampled in the Observed region, after the flop had already changed");
    else $display("PASS: #1step recorded the value from before the edge");
    $finish;
  end
endmodule

Prints: monitor recorded 00 PASS: #1step recorded the value from before the edge

Spec Misquote

"#1step means one nanosecond before the edge."

1step is one unit of the global time precision. The standard defines the sample as the Preponed value, not as a time offset you can tune.

Source IEEE 1800-2017 §14.4

Spec Misquote

"Without a skew the default is #0."

The default input skew is #1step and the default output skew is #0. A default clause in the clocking block can change them.

Source IEEE 1800-2017 §14.3

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