← Design Verification Interviews
Interview Question · Concept
What Interfaces and Modports Give You
The Question
The interviewer asks
Why use an interface instead of a list of ports, and what does a modport add on top?
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Reveal the Model Answer
An interface bundles a protocol's signals in one place. It can also hold clocking blocks, tasks and assertions. Adding a signal then means one edit instead of changing every port list. A modport declares one side's view of that bundle, such as which signals a driver writes and a monitor only reads. The compiler then rejects a write through an input-only modport, which a plain interface port never checks.
bus shared by a testbench, a sink DUT and a monitor. Arrows show signal values: an arrow into bus means that block drives the signal; an arrow out of it means a block reads it.- One instance
rd_if bus (clk);creates the three wires once. The DUT gets thesinkview, the monitor gets themonitorview, and the testbench drives the source side. - The source offerst=10 (illustrative)
At the falling edge at 10, the testbench raises
rvalidwith a1. Only the source side drives these two signals.Follow the calls, values and waits
- data rvalid=1, rdata=a1: tb initial block → rd_if bus
- The sink stallst=15 (illustrative)
The DUT holds
rreadyat 0. At the edge at 15, the testbench reads it and keeps its offer; the monitor sees an offer but no transfer.Follow the calls, values and waits
- data rready=0: sink_dut → rd_if bus
- data rready=0: rd_if bus → tb initial block
- The beat movest=25 (illustrative)
rreadyis 1 before the edge at 25, so a1 transfers. The monitor only reads the bundle and prints the transfer.Follow the calls, values and waits
- data rready=1: sink_dut → rd_if bus
- data transfer a1: rd_if bus → rd_monitor
- The monitor tries to drive
Add
assign bus.rready = 1;to the monitor and the build stops. In themonitorview,rreadyis an input.More context
This is the opening story caught at compile time: a monitor copied from a driver can no longer hold the channel ready.
Follow the calls, values and waits
- call drive rready: rd_monitor → Compile error
Read the diagram as text
- tb initial block: source side: drives rvalid, rdata
- rd_if bus: rvalid, rready, rdata
- sink_dut: rd_if.sink: drives rready
- rd_monitor: rd_if.monitor: inputs only
- Compile error: Attempt to drive input-only modport
- tb initial block → rd_if bus: rvalid, rdata
- sink_dut → rd_if bus: rready
- rd_if bus → tb initial block: rready
- rd_if bus → rd_monitor: all three, read only
- rd_monitor → Compile error: assign bus.rready
The modports decide which arrows may exist. Between bus and the monitor, the only legal arrow points toward the monitor.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Fresher)
A good fresher answer explains the benefit of bundling with an example, such as adding one signal in one place. It says a modport sets the signal directions for each side.
What Interviewers Listen For (Junior)
A good junior answer gives the monitor an input-only modport, so a stray write fails to compile. It knows a modport adds no timing of its own.
What Interviewers Listen For (Senior)
A good senior answer designs the interface as the agent's contract, with a modport and a clocking block for each role. It puts the protocol assertions inside, so every bench that uses the interface gets the checks.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyProve ItBreak ItCompareScale It
- What Interfaces and Modports Give You
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WhyWhy Classes Need Virtual InterfacesL1 Junior
Why can't a driver class simply contain the interface instance? Why the
virtualkeyword?2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Interfaces are static, elaborated hierarchy, while class objects are created at run time, so a class cannot instantiate one. A virtual interface is a variable holding a reference to an existing interface instance. The bench assigns it before use, so one driver class can be pointed at any instance of the interface.
Self-Check
Tick each key point you covered in your answer.
Misconception
"
virtualmeans the same as invirtual function: it can be overridden."Here it means a reference to an interface instance; it has nothing to do with method dispatch.
Source IEEE 1800-2017 §25.9
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Break ItA Virtual Interface That Was Never SetL1 Junior
The test crashes with a null access the first time the driver touches
vif.valid. What happened and how do you fail faster?2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
The virtual interface variable is null until something assigns it, and nothing did. Check it where it is received, for example right after the configuration lookup, and stop with a message naming the agent. The failure then points at the missing assignment, not at the first signal access.
Self-Check
Tick each key point you covered in your answer.
Misconception
"An unassigned virtual interface points at the first instance of that interface."
It is null until assigned; there is no default binding to any instance.
Source IEEE 1800-2017 §25.9
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CompareAn Interface vs a Packed Struct PortL1 JuniorL2 Mid-Level
Compare passing a bus as an interface with passing it as a packed struct port.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
A packed struct port is a plain vector with named fields. Every field flows in one direction, and it synthesises like any port. An interface can mix directions through modports and can carry clocking blocks, tasks and assertions, which is why testbenches use it. Many RTL teams use structs for one-way buses and interfaces where both directions travel together.
Self-Check
Tick each key point you covered in your answer.
Misconception
"Interfaces cannot be synthesised."
Synthesis tools accept interfaces with modports; what they ignore are verification-only contents such as clocking blocks.
Source Sutherland, RTL Modeling with SystemVerilog for Simulation and Synthesis, ch. 10
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Prove ItSolve 6.1.1: Count the Real TransfersSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
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Scale ItPutting Protocol Checks in the InterfaceL2 Mid-LevelL3 Senior
Your team has twelve agents on the same bus protocol. Where do the protocol assertions live, and why?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Inside the interface, or in a checker bound to it, so every instance of the bus is checked in every bench. Each agent then reuses the checks with no extra work, and a block-level bench and a chip-level bench check the same rules. Give the checks a switch for the rare test that drives illegal traffic on purpose, rather than deleting them.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Senior)
A good senior answer puts the checks where every instance gets them. It plans the allowed exception, such as an enable or a per-test assertion control, instead of making copies.
Wrong Altitude
"Each agent's monitor checks the protocol in class code."
Twelve copies drift apart, and a bench without the agent loses the checks. Formal tools also cannot reuse class code the way they reuse assertions.
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Missed Corner
"A monitor only reads, so it cannot disturb the bus."
Through a plain interface port any module can write any signal. In the twin a forgotten debug write in the monitor clears valid under the driver.
Run It
A monitor connected through a plain interface port, with one stray write.
valid=0 FAIL: through a plain interface port the monitor overwrote valid and nothing stopped itMisconception
"A modport makes a separate copy of the signals for each side."
Modports are views of the same signals with directions attached; there is one valid, seen by every modport.
Source IEEE 1800-2017 §25.5
Spec Misquote
"The modport's directions also fix when signals are sampled."
Modports carry no timing. Sampling and drive times come from a clocking block, which a modport can list.
Source IEEE 1800-2017 §25.5