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Interview Question · Concept

Is Logic a Wire or a Reg?

L0 FresherL1 Juniorsystemverilogdata typesnets

The interviewer asks

Is logic a wire or a reg? When do you still have to write wire?

Reveal the Model Answer

logic is a data type, not a kind of object. Declared alone in a module, it makes a variable. wire logic makes a net. Many procedural statements may write a variable, but only one continuous driver may drive it. A net combines (resolves) several drivers. So write wire for multiply driven or bidirectional signals, such as a tri-state bus or an inout, and logic for the rest.

A Net Resolves Its Drivers; a Variable Allows OneTop: two continuous drivers on a net, as in the run. Bottom: a variable. Arrows show values being driven or written.
A net resolves its drivers; a variable allows oneTop: two continuous drivers on a net, as in the run. Bottom: a variable. Arrows show values being driven or written. component assign bus = 1'b0 continuous driver 1 component assign bus = 1'b1 continuous driver 2 component wire logic bus a net: it combines(resolves) all itsdrivers component bus = x 0 and 1 at the samestrength resolve to x component initial and alwaysblocks procedural writes, asmany as you like component logic v a variable: holds thelast value written component assign v = ... one continuous driverat most; a second oneis a compile error drives 0drives 1resolveswritesonly one
Read the diagram as text
  • assign bus = 1'b0: continuous driver 1
  • assign bus = 1'b1: continuous driver 2
  • wire logic bus: a net: it combines (resolves) all its drivers
  • bus = x: 0 and 1 at the same strength resolve to x
  • initial and always blocks: procedural writes, as many as you like
  • logic v: a variable: holds the last value written
  • assign v = ...: one continuous driver at most; a second one is a compile error
  • assign bus = 1'b0 → wire logic bus: drives 0
  • assign bus = 1'b1 → wire logic bus: drives 1
  • wire logic bus → bus = x: resolves
  • initial and always blocks → logic v: writes
  • assign v = ... → logic v: only one

Use wire where several drivers meet, such as a tri-state bus. Use a logic variable everywhere else.

A net with two continuous drivers that disagree.

RUNIcarus Verilog · in your browser
Edit the code, then run it

        
Expected: bus=x

        
        
      

          
Self-Check
Tick each key point you covered in your answer.


What Interviewers Listen For (Fresher)
A good fresher answer keeps two ideas apart: the data type (logic holds four values) and the object kind (net or variable). It gives a tri-state bus as the place where wire is needed.


        

      

    

    
  

    

    

    
Cross-Questions

    
Where the interviewer goes next. Open a node to practise that follow-up.

    
WhyWhat IfBreak ItCompare

    
    
      
  1. Is Logic a Wire or a Reg?
    2. 
      
  2. 
    
    WhyWhy a Variable Allows One Continuous DriverL1 Junior
      
    
      
    Why does the language let a net have many drivers but a variable only one continuous driver?
    
      
    
    
    
    
      
      
    Reveal the Model Answer
        
    A variable simply holds the last value written to it; it has no rule for combining two simultaneous drivers. A net is modelled as a wire with a resolution function that merges drivers by value and strength. Forbidding a second continuous driver on a variable turns an accidental short into a compile error instead of a silent last-writer-wins race.
    
          
    Self-Check
    Tick each key point you covered in your answer.
    


        
    
      
    
    
    
    
  
    
      
    
    
    Half-Truth
    
    
    "Two procedural blocks writing one logic are illegal too."
    
    
    Several always or initial blocks may write one variable; that is legal but racy. The single-driver rule covers continuous assignments and port outputs, and always_ff/always_comb add their own one-writer rule.
    
    
    Source IEEE 1800-2017 §9.2.2
    
  
    
    
    3. 

  3. 
    
    What IfTwo Always_ff Blocks Writing One VariableL1 JuniorL2 Mid-Level
      
    
      
    What if two always_ff blocks both write the same logic variable?
    
      
    
    
    
    
      
      
    Reveal the Model Answer
        
    That is two procedural writers, which plain always blocks would allow. always_ff adds a rule: a variable it writes must not be written by any other process. So the tool reports an error. With plain always blocks, the last write in each time step would win a race.
    
          
    Self-Check
    Tick each key point you covered in your answer.
    


        
    
      
    
    
    
    
  
    
      
    
    
    Spec Misquote
    
    
    "logic only forbids two continuous drivers, so two always_ff blocks are fine."
    
    
    always_ff adds its own rule: no other process may write its variables. The tool rejects the second block.
    
    
    Source IEEE 1800-2017 §9.2.2.4
    
  
    
    
    4. 

  4. 
    
    What IfWhat Kind of Object Is an Input Logic Port?L2 Mid-Level
      
    Asked if they say ports should be declared logic
    
      
    A port is declared input logic [7:0] d. Is d a net or a variable inside the module? And output logic [7:0] q?
    
      
    
    
    
    
      
      
    Reveal the Model Answer
        
    When the kind is left out, an input port with a data type becomes a net. So d is a wire of type logic. An output port with a data type defaults to a variable, so q can be written procedurally but by only one driver. That is why output logic catches two blocks driving the same output, while inputs still resolve like wires.
    What a port declaration makes inside the module
    
        
    DeclarationObject kindWho may write it
    
        
    input logic [7:0] dNet (wire logic)The outside driver; drivers resolve like a wire
    output logic [7:0] qVariableProcedural code, or one continuous driver
    inout wire [7:0] ioNetSeveral drivers, for example tri-state buffers
    
      
    When the declaration leaves out the kind, inputs and inouts become nets and outputs become variables.
    
          
    Self-Check
    Tick each key point you covered in your answer.
    


        
    
      
    
    
    
    
  
    
      
    
    
    Spec Misquote
    
    
    "logic on a port always makes a variable."
    
    
    The default kind depends on the direction. Inputs and inouts become nets; only outputs become variables.
    
    
    Source IEEE 1800-2017 §23.2.2.3
    
  
    
    
    5. 

  5. 
    
    Break ItA Port Typo That Became a WireL1 JuniorL2 Mid-Level
      
    
      
    A block's output is stuck at 0000000z although the testbench drives data_in correctly. The instance connects .d(dta_in). Why did it compile, and how do you stop it happening again?
    log
    q=0000000z
(no compile warning; data_in = 8'h5a in the testbench)
    
      
    
    
    
    
      
      
    Reveal the Model Answer
        
    An undeclared name in a port connection silently creates an implicit one-bit net, so dta_in is a new floating wire. Put ` default_nettype none ` at the top of every file, which turns implicit nets into compile errors, and restore  default_nettype wire `` at the end if legacy code needs it.
    
          
    Self-Check
    Tick each key point you covered in your answer.
    


        
    
      
    
    
    
    
  
    
      
    
    
    Missed Corner
    
    
    "The compiler would have warned about an unknown signal."
    
    
    Implicit nets are legal Verilog, so a compiler may accept them silently. The twin compiles with no message and passes z through.
    
    
    Run It
      
    A one-letter typo in a port connection, compiled with default settings.
    
        
    RUNIcarus Verilog · in your browser
    
        
    Edit the code, then run it
    
          
    
          
    
          
    
        
    Expected: q=0000000z FAIL: the typo became an implicit 1-bit net and nothing complained
    
        
        
      
    
      
    See the Fix
    `default_nettype none
module sink(input logic [7:0] d, output logic [7:0] q);
  assign q = d;
endmodule
module tb;
  logic [7:0] data_in = 8'h5a, q;
  sink u (.d(data_in), .q(q));   // spelled right; a typo is now a compile error
  initial #1 begin
    $display("q=%b", q);
    if (q !== 8'h5a) $display("FAIL: the typo became an implicit 1-bit net and nothing complained");
    else $display("PASS: the port carries data_in");
  end
endmodule

    Prints: q=01011010 PASS: the port carries data_in
    
    
    
  
    
    
    6. 

  6. 
    
    CompareUwire or a Variable for Single-Driver ChecksL2 Mid-Level
      
    
      
    You want to catch a second driver on an internal signal. Compare declaring it as uwire with declaring it as a logic variable.
    
      
    
    
    
    
      
      
    Reveal the Model Answer
        
    Both make a second continuous driver an error. A uwire is still a net, so it can connect module ports like any wire. But procedural code cannot write it. A logic variable can also be written from a procedural block, which is often what an RTL signal needs.
    
          
    Self-Check
    Tick each key point you covered in your answer.
    


        
    
      
    
    
    
    
  
    
      
    
    
    Spec Misquote
    
    
    "uwire is a Verilator extension."
    
    
    It is a standard net type, an unresolved wire that permits a single driver.
    
    
    Source IEEE 1800-2017 §6.6.2
    
  
    
    
    7. 
    

  

    
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.

    
Half-Truth

    
"A reg is a register."

    
It is a register only when a clocked block writes it. The twin writes a reg from always @* and it follows its input with no clock at all.

    
Run It
      
A reg written from always @*, with no clock edge in the whole run.

        
RUNIcarus Verilog · in your browser

        
Edit the code, then run it

          

          

          

        
Expected: y=1 FAIL: y followed a with no clock, so this reg is combinational logic

        
        
      

      
See the Fix
module tb;
  logic clk = 0, a = 0, b = 1;
  reg   y;
  // The belief: a reg is a register, so y changes only on a clock edge.
  always @(posedge clk) y = a & b;   // the fix: a clocked block makes the flop
  initial begin
    #1 a = 1;                 // no clock edge ever happens
    #1 $display("y=%b", y);
    if (y === 1'b1) $display("FAIL: y followed a with no clock, so this reg is combinational logic");
    else $display("PASS: without an edge the flop kept its value");
  end
endmodule

Prints: y=x PASS: without an edge the flop kept its value

    

  

    
Misconception

    
"logic resolves two drivers the same way a wire does."

    
A logic variable with two continuous assignments is illegal; only a net has a resolution function.

    
Source IEEE 1800-2017 §6.5

  

    
Tool as Truth

    
"Verilator compiled two assigns to my logic, so it is legal."

    
Verilator 5.052 accepted it and printed one driver's value; Icarus 12 refuses it with "cannot have multiple drivers". The standard decides, not the tool that let it through.

    
Source IEEE 1800-2017 §6.5; measured: Verilator 5.052 compiles it, Icarus 12 rejects it

  

    
Buzzword Without Mechanism

    
Lists "wire is for combinational, reg is for sequential".

    
That is a coding guideline from Verilog-2001 days, not the language rule. The rule is about how many drivers an object may have.

  

    
Learn It, Then Prove It