The Regions of a Time Slot

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WhyWhat IfProve ItBreak ItCompare

1. The Regions of a Time Slot
2. WhyWhy Nonblocking Makes Process Order IrrelevantL1 Junior

   Two clocked always blocks read each other's outputs. Why does <= make the result independent of which block the simulator runs first?

   Reveal the Model Answer

   With <=, neither block changes a variable during the Active region; each only reads and schedules. Whichever block runs first, both read the same pre-edge values. The updates all land later, in the NBA region. With =, the first block to run changes its output before the second reads it. So the order decides the answer.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 With <=, neither block changes a variable during the Active region; each only reads and schedules. Key point 2 Whichever block runs first, both read the same pre-edge values. Key point 3 The updates all land later, in the NBA region. Key point 4 With =, the first block to run changes its output before the second reads it. Key point 5 So the order decides the answer.

   What Interviewers Listen For (Junior)

   A good junior answer walks through both orders of the two blocks. It shows they give the same values with <= and different values with =.

   Misconception

   "<= makes the simulator run all always blocks at the same instant."

   Processes still run one after another. The order stops mattering because no process sees another one's update until the NBA region.

   Source IEEE 1800-2017 §4.9.4, §4.7

   • Lesson 6.2Scheduling Regions and Nonblocking Updates
3. Break ItBreaking a Clocked Block with a Blocking TemporaryL1 JuniorL2 Mid-Level

   A clocked block computes tmp = a + b; and then sum <= tmp;. Another always block also reads tmp at the same edge. What can go wrong?

   always @(posedge clk) begin
     tmp = a + b;
     sum <= tmp;
   end
   always @(posedge clk) observed <= tmp;

   Reveal the Model Answer

   Inside the block the code is fine, because tmp is a local temporary. The bug is the second reader: it may run before or after the first block in the same Active region. So it sees either the old or the new tmp. Keep blocking temporaries local to their block, or declare them inside it. Share only flop outputs written with <=.

   1. The edge wakes botht=5 (illustrative)

      The rising edge at t=5 wakes the driver and the monitor. Both are now waiting to run in the Active region of the same time step.

      Follow the calls, values and waits

      1. call driver: Rising edge → Active region
      2. call monitor: Rising edge → Active region
   2. Order A: driver firstt=5 (illustrative)

      If the scheduler runs the driver first, rdata is already a1 when the monitor reads it. The monitor sees the new beat.

      Follow the calls, values and waits

      1. call run: Active region → Racy driver
      2. data rdata = a1: Racy driver → racy_bus pins
      3. call run: Active region → Raw monitor
      4. data reads a1: racy_bus pins → Raw monitor
   3. Order B: monitor firstt=5 (illustrative)

      If it runs the monitor first, the monitor reads 00, the value from before the edge. The standard allows both orders.

      Follow the calls, values and waits

      1. call run: Active region → Raw monitor
      2. data reads 00: racy_bus pins → Raw monitor
      3. call run: Active region → Racy driver
      4. data rdata = a1: Racy driver → racy_bus pins
   4. Move the write off the edget=5 to t=7 (illustrative)

      A drive through drv_cb with output skew 2 lands at t=7. At t=5 every reader sees 00, in any order, so the race is gone.

      More context

      The DUT reads the pins at the same edge, so it is exposed to the race in exactly the same way as the monitor.

      Follow the calls, values and waits

      1. data reads 00: racy_bus pins → Raw monitor
      2. data rdata = a1 at t=7: Racy driver → racy_bus pins

   Read the diagram as text

   • Rising edge: t=5: clk becomes 1
   • Active region: woken processes; order not specified
   • Racy driver: rdata = a1 after @(posedge clk)
   • Raw monitor: reads rdata after @(posedge clk)
   • racy_bus pins: rvalid, rdata

   • Rising edge → Active region: wakes both
   • Active region → Racy driver: runs
   • Active region → Raw monitor: runs
   • Racy driver → racy_bus pins: writes
   • racy_bus pins → Raw monitor: reads

   A result that depends on which process runs first is not a result. Remove the race; do not pick a winner.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Inside the block the code is fine, because tmp is a local temporary. Key point 2 The bug is the second reader: it may run before or after the first block in the same Active region. Key point 3 So it sees either the old or the new tmp. Key point 4 Keep blocking temporaries local to their block, or declare them inside it. Key point 5 Share only flop outputs written with <=.

   Half-Truth

   "Mixing = and <= in one clocked block is always illegal."

   The language allows it. A blocking temporary that only its own block reads is a common, safe pattern. The danger is a temporary that another process reads at the same edge.

   • Lesson 6.2Scheduling Regions and Nonblocking Updates
   • Lesson 6.7Debug Case: A Racing Monitor
4. CompareProgram Blocks vs a Module Bench with Clocking BlocksL2 Mid-Level

   Compare writing the testbench in a program block with writing it in a module that drives through clocking blocks.

   Reveal the Model Answer

   A program runs its code in the Reactive region, after the design has settled, so its reads never race with design updates. A clocking block gets the same effect at the signal level. It samples inputs before the edge and drives outputs at a skew after it, from ordinary module or class code. Most class-based benches, UVM included, use modules plus clocking blocks, because programs add restrictions such as no always blocks.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 A program runs its code in the Reactive region, after the design has settled, so its reads never race with design updates. Key point 2 A clocking block gets the same effect at the signal level. Key point 3 It samples inputs before the edge and drives outputs at a skew after it, from ordinary module or class code. Key point 4 Most class-based benches, UVM included, use modules plus clocking blocks, because programs add restrictions such as no always blocks.

   Misconception

   "UVM requires a program block."

   UVM classes are started from a module's initial block; nothing in the library depends on a program.

   Source IEEE 1800-2017 §24.3

   • Lesson 6.2Scheduling Regions and Nonblocking Updates
   • Lesson 6.3Clocking Blocks and Sampled Views
5. WhyWhy Program Blocks Fell Out of UseL2 Mid-LevelL3 Senior

   Program blocks were added to SystemVerilog to fix testbench races. Why do most teams no longer use them?

   Reveal the Model Answer

   Clocking blocks already remove the TB-to-DUT race at the signal boundary, and that is where the race actually lives. Programs add awkward rules on top, such as special rules for when the simulation ends. They also mix poorly with class-based code started from modules. The industry settled on modules, classes and clocking blocks.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Clocking blocks already remove the TB-to-DUT race at the signal boundary, and that is where the race actually lives. Key point 2 Programs add awkward rules on top, such as special rules for when the simulation ends. Key point 3 They also mix poorly with class-based code started from modules. Key point 4 The industry settled on modules, classes and clocking blocks.

   What Interviewers Listen For (Senior)

   A good senior answer treats it as a cost and benefit decision. It names the race that neither construct solves: two threads inside the bench.

   Spec Misquote

   "Programs were removed from the standard."

   They are still in IEEE 1800-2017; teams stopped choosing them.

   Source IEEE 1800-2017 §24.1

   • Lesson 6.3Clocking Blocks and Sampled Views
6. What IfWhat an Assertion Sees vs What Its Action Block SeesL2 Mid-Level

   Asked if they mention assertions

   What if an assertion's fail action prints the signals it checked? Which values appear?

   Reveal the Model Answer

   The assertion decided using Preponed samples, but its action block runs later, in Reactive, after the NBA updates. Printing a signal there shows its new value, which can contradict the failure. Print $sampled(sig) to show what the assertion actually saw.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The assertion decided using Preponed samples, but its action block runs later, in Reactive, after the NBA updates. Key point 2 Printing a signal there shows its new value, which can contradict the failure. Key point 3 Print $sampled(sig) to show what the assertion actually saw.

   Misconception

   "The action block runs at the moment of sampling, so it prints the checked values."

   Sampling and the action block are in different regions of the slot; flops written with <= at that edge have already changed.

   Source IEEE 1800-2017 §4.4.2.6

   • Lesson A1.2Clocks and Sampling
   • Lesson 6.6Assertions and Protocol Checks
7. Break ItA Loop That Never Advances TimeL1 JuniorL2 Mid-Level

   How can two always blocks stop simulation time from ever advancing?

   Reveal the Model Answer

   Suppose each block wakes on a change that the other makes, with no delay between. The two blocks keep creating new events in the same time slot, so time never moves on. An accidental combinational loop such as assign a = ~a; does it too. Simulators detect it with an iteration limit or appear to hang.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Suppose each block wakes on a change that the other makes, with no delay between. Key point 2 The two blocks keep creating new events in the same time slot, so time never moves on. Key point 3 An accidental combinational loop such as assign a = ~a; does it too. Key point 4 Simulators detect it with an iteration limit or appear to hang.

   Misconception

   "A #0 in the loop breaks it."

   #0 stays inside the same time slot, so the loop still never reaches the next time. Only a nonzero delay or breaking the dependency helps.

   Source IEEE 1800-2017 §4.4.2.3

   • Lesson 6.2Scheduling Regions and Nonblocking Updates
8. Prove ItSolve 6.2.1: The Pipeline That Lost a StageSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem 6.2.1