Interview Question · Code Reading

The Unknown Select That Picked a Side

L1 JuniorL2 Mid-Levelsystemverilogfour statex propagation

The interviewer asks

The select comes out of reset as x. What does this print, and what would real hardware do?

systemverilog

logic sel, a = 1, b = 0, y;
initial begin
  sel = 1'bx;                 // an unreset select
  if (sel) y = a;
  else     y = b;
  $display("y=%b", y);
end

Reveal the Model Answer

It prints y=0. An if treats an x condition as false and takes the else branch. So the unknown select gives a clean value, and the x disappears. Real hardware would pick one input or the other, possibly a different one on each chip. This X-optimism can hide a missing reset, so check the select with $isunknown or an assertion instead of trusting the output.

An x Select in Simulation and in SiliconThe snippet's select comes out of reset as x. Arrows show where the value goes in RTL simulation and in real hardware.

Read the diagram as text

sel = x: never reset
Check the select: $isunknown(sel) or an assertion catches it here
if (sel) y = a; else y = b;: an x condition counts as false
Simulation: y = 0: a clean value; the x is gone
Real hardware: the mux sees a real 0 or 1
y = 1 or y = 0: can differ from chip to chip

sel = x → if (sel) y = a; else y = b;: RTL simulation
if (sel) y = a; else y = b; → Simulation: y = 0: else branch
sel = x → Real hardware: silicon
Real hardware → y = 1 or y = 0
Check the select → sel = x: flags x

The simulation shows one clean answer, but silicon may show the other. Check the select, not the output.

Self-Check

Tick each key point you covered in your answer.

Key point 1 It prints y=0. Key point 2 An if treats an x condition as false and takes the else branch. Key point 3 So the unknown select gives a clean value, and the x disappears. Key point 4 Real hardware would pick one input or the other, possibly a different one on each chip. Key point 5 This X-optimism can hide a missing reset, so check the select with $isunknown or an assertion instead of trusting the output.

What Interviewers Listen For (Junior)

A good junior answer predicts y=0 and explains that if takes the false branch on x. It suggests an $isunknown check on the select.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyProve ItCompareScale It

The Unknown Select That Picked a Side

CompareIf Versus the Conditional Operator on an UnknownL1 JuniorL2 Mid-Level

Compare if (sel) y = a; else y = b; with y = sel ? a : b; when sel is x.

Reveal the Model Answer

The if takes the else branch and gives b. With an x condition, the conditional operator evaluates both sides and merges them bit by bit. Equal bits stay, and differing bits become x. So sel ? 1 : 0 gives x, and sel ? 4'b1100 : 4'b1010 gives 1xx0. The run shows all three.

The same x select, three ways

Code	Result	Why
`if (sel) y = 1; else y = 0;`	`0`	The `else` branch runs
`sel ? 1 : 0`	`x`	Both sides are merged; the bits differ
`sel ? 4'b1100 : 4'b1010`	`1xx0`	Equal bits stay; different bits become x

The results are the output of the run on this question.

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Edit the code, then run it

Expected: if: 0 ternary: x ternary on vectors: 1xx0

module tb;
  logic sel, a = 1'b1, b = 1'b0, y_if, y_tern;
  logic [3:0] p = 4'b1100, q = 4'b1010, m;
  initial begin
    sel = 1'bx;
    if (sel) y_if = a; else y_if = b;
    y_tern = sel ? a : b;
    m = sel ? p : q;
    $display("if: %b  ternary: %b  ternary on vectors: %b", y_if, y_tern, m);
  end
endmodule

Self-Check

Tick each key point you covered in your answer.

Key point 1 The if takes the else branch and gives b. Key point 2 With an x condition, the conditional operator evaluates both sides and merges them bit by bit. Key point 3 Equal bits stay, and differing bits become x. Key point 4 So sel ? 1 : 0 gives x, and sel ? 4'b1100 : 4'b1010 gives 1xx0. Key point 5 The run shows all three.

Misconception

"The conditional operator gives all x when the condition is x."

Bits where both sides agree stay known. 1xx0 keeps the outer bits because both inputs have them.

Source IEEE 1800-2017 §11.4.11

Lesson 1.7Debug Case: The X That Became Zero

WhyWhy an Unknown Condition Is Treated as FalseL1 Junior
Why does the language pick the else branch for an x condition instead of making everything unknown?

Reveal the Model Answer

A procedural if must run one branch or the other. It cannot run both branches and merge what their statements did. The rule picks "not true", which is cheap and deterministic but optimistic. The conditional operator can merge because it produces a value, not side effects.

Self-Check
Tick each key point you covered in your answer.
Key point 1 A procedural if must run one branch or the other. Key point 2 It cannot run both branches and merge what their statements did. Key point 3 The rule picks "not true", which is cheap and deterministic but optimistic. Key point 4 The conditional operator can merge because it produces a value, not side effects.

Misconception

"It picks a branch at random, like hardware."

The rule is deterministic: x and z conditions always count as false.

Source IEEE 1800-2017 §12.4
- Lesson 1.7Debug Case: The X That Became Zero
CompareA Case Statement on an Unknown SelectL1 JuniorL2 Mid-Level
Compare if with case for an x select. Which branch does the case take?

Reveal the Model Answer

case compares with exact matching, so an x select matches only an item that has x in the same bits. Normally no item does, so the default runs, or nothing runs. Like if, it picks one path and hides the x. casex treats x bits as wildcards, so it can hide the x even more.

Self-Check
Tick each key point you covered in your answer.
Key point 1 case compares with exact matching, so an x select matches only an item that has x in the same bits. Key point 2 Normally no item does, so the default runs, or nothing runs. Key point 3 Like if, it picks one path and hides the x. Key point 4 casex treats x bits as wildcards, so it can hide the x even more.

Misconception

"case passes the x on, because it compares bit by bit."

The comparison is exact, x against x. An x select falls through to the default, so the output looks clean.

Source IEEE 1800-2017 §12.5
- Lesson 1.7Debug Case: The X That Became Zero
- Problem 1.7.2Repair the Transaction Field
Scale ItReset and X Sign-Off for a BlockL3 Senior
How do you sign off that a block has no X bugs, given that RTL simulation is optimistic?

Reveal the Model Answer

Combine three things. Assertions check that every valid output and every state register is known a few cycles after reset. A reset test runs on a four-state simulator with no forced initial values. Gate-level runs cover the reset paths, and their pessimism shows what RTL hid. Review every waiver, because a pessimistic false x and a real one look the same.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Combine three things. Key point 2 Assertions check that every valid output and every state register is known a few cycles after reset. Key point 3 A reset test runs on a four-state simulator with no forced initial values. Key point 4 Gate-level runs cover the reset paths, and their pessimism shows what RTL hid. Key point 5 Review every waiver, because a pessimistic false x and a real one look the same.

What Interviewers Listen For (Senior)
A good senior answer gives a clear exit test: every output is known a few cycles after reset, on a four-state simulator. It also admits that pessimistic false alarms cost review time.

Wrong Altitude

"Initialise every flop in the testbench and the problem goes away."

Forcing initial values hides exactly the missing resets you were asked to find.
- Lesson 1.7Debug Case: The X That Became Zero
Prove ItSolve 1.7.2: Repair the Transaction FieldSimulator-graded

Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
Open Problem 1.7.2

What People Get Wrong

Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.

Misconception

"An x select makes the output x, so the bug would show up."

Only some constructs propagate x. In an if, the x condition is false; the twin prints a clean y=0.

Run It

An unknown select through an if/else.

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Edit the code, then run it

Expected: y=0 FAIL: if treats x as false, so y took b and the x vanished

module tb;
  logic sel, a = 1'b1, b = 1'b0, y;
  initial begin
    sel = 1'bx;
    if (sel) y = a; else y = b;   // the belief: an x select makes y unknown
    $display("y=%b", y);
    if (y !== 1'bx) $display("FAIL: if treats x as false, so y took b and the x vanished");
  end
endmodule

See the Fix

module tb;
  logic sel, a = 1'b1, b = 1'b0, y;
  initial begin
    sel = 1'bx;
    if ($isunknown(sel)) begin y = 'x; $display("PASS: the unknown select is reported, y=%b", y); end
    else if (sel) y = a; else y = b;
  end
endmodule

Prints: PASS: the unknown select is reported, y=x

Missed Corner

"Check if (rdata != exp) error++;; that catches any mismatch."

With an x bit, != returns x and the if skips the error, so an x bus passes the check. !== compares x bits too.

Run It

A scoreboard check with != on a bus that carries x bits.

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Edit the code, then run it

Expected: errors=0 FAIL: rdata != exp is x, if treats x as false, and the x bus passed

module tb;
  logic [7:0] rdata = 8'bxxxx_0101, exp = 8'h05;
  int errors = 0;
  initial begin
    // The belief: a != check reports any difference, x included.
    if (rdata != exp) errors++;
    $display("errors=%0d", errors);
    if (errors == 0) $display("FAIL: rdata != exp is x, if treats x as false, and the x bus passed");
    else $display("PASS: !== compares x bits too and caught the bus");
  end
endmodule

See the Fix

module tb;
  logic [7:0] rdata = 8'bxxxx_0101, exp = 8'h05;
  int errors = 0;
  initial begin
    // The belief: a != check reports any difference, x included.
    if (rdata !== exp) errors++;
    $display("errors=%0d", errors);
    if (errors == 0) $display("FAIL: rdata != exp is x, if treats x as false, and the x bus passed");
    else $display("PASS: !== compares x bits too and caught the bus");
  end
endmodule

Prints: errors=1 PASS: !== compares x bits too and caught the bus

Misconception

"RTL simulation is pessimistic about x, so if RTL passes, gates pass."

RTL if and case are optimistic: they resolve x to a branch. Gate-level models can be pessimistic instead, so the two can disagree on the same stimulus.

Source Sutherland, RTL Modeling with SystemVerilog for Simulation and Synthesis, appendix C

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