← Design Verification Interviews
Interview Question · Project Defence
Defending the Assertion Plan for a Block
- Asked at NVIDIA
- Likely at Synopsys
- Likely at Samsung
The Question
The interviewer asks
Walk me through the assertion plan you wrote for your last block. Which properties did you write, where did they live, and how did you know they were enough?
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Reveal the Model Answer
A strong answer starts from the spec, not the RTL. Interface rules go in the interface or a bound checker, so every bench gets them. Internal invariants, such as FIFO limits and one-hot states, sit next to the logic or are bound in. Each property has an antecedent cover and a line in the verification plan. "Enough" means every spec rule maps to a property or a scoreboard check, and every cover was hit.
Read the diagram as text
- Spec rules: Every sentence that can be checked
- Interface rules: In the interface or a bound checker
- Internal invariants: FIFO limits, one-hot states; bound in
- Scoreboard checks: End-to-end data
- Antecedent covers: Show each rule was really exercised
- Plan line per rule: Rule, check, cover and status
- Spec rules → Interface rules
- Spec rules → Internal invariants
- Spec rules → Scoreboard checks
- Interface rules → Antecedent covers
- Internal invariants → Antecedent covers
- Antecedent covers → Plan line per rule: hit in regression
- Scoreboard checks → Plan line per rule
The plan is enough when every spec rule has a check and every cover was hit.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Senior)
A good senior answer gives a reason for where each property lives and shows how spec rules map to properties. It names one bug the assertions found first.
What Interviewers Listen For (Staff)
A good staff answer talks about cost and reuse across projects. It says which properties went to formal, how tool gaps were handled, and what the team changed after a missed bug.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItBreak ItCompareScale It
- Defending the Assertion Plan for a Block
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WhyWhy Assertions Come from the SpecL2 Mid-LevelL3 Senior
Why should assertions be written from the specification instead of from reading the RTL?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
An assertion written from the RTL describes what the code does. So it agrees with the code even when the code is wrong. An assertion written from the spec is an independent second opinion. That independence is the whole value of a check.
Self-Check
Tick each key point you covered in your answer.
Half-Truth
"The designer knows the RTL best, so the designer should write every assertion."
Designer assertions catch local mistakes well. Spec-level rules need someone reading the spec separately, or both sides share the same mistake.
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What IfWhen the Designer Says Read the RTLL2 Mid-LevelL3 Senior
What if the spec is vague on a rule, and the designer tells you to read the RTL?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Do not copy the RTL into the assertion. Write the question down and get the architect to answer it in the spec or a decision log. Then write the assertion from that answer. If the RTL disagrees, one of them has a bug, and you found it early.
Self-Check
Tick each key point you covered in your answer.
Misconception
"The RTL is the real spec, so write the assertion from it."
Then the assertion agrees with the code even when the code is wrong. A check needs an independent source.
Source Mehta, SystemVerilog Assertions and Functional Coverage (3rd ed.), §2.2
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CompareOrdering Checks: Assertions or the Scoreboard?L3 Senior
For a block with outstanding, tagged transactions, which ordering and completion rules do you put in assertions and which in the scoreboard?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Assertions take the local, cycle-level rules: an ID is not reused while outstanding, every response matches an outstanding ID, deadlines are met. They report the exact cycle and also run in formal. The scoreboard takes end-to-end data correctness and anything needing a reference model. Overlap is deliberate: a lost response should be caught by both, at different distances from the bug.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Senior)
A good senior answer splits the rules by how local they are and by reuse in formal. It wants both the assertions and the scoreboard to catch a lost response, on purpose.
Wrong Altitude
"The scoreboard already checks everything, so assertions are redundant."
A scoreboard reports a missing response at the end of the test, far from the cause. An assertion names the cycle, and only properties carry over to formal.
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Scale ItAssertion Quality Sign-Off Across an IPL3 SeniorL4 Staff
Your IP has several hundred assertions. How do you show in sign-off that they actually checked something?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Pair every implication with an antecedent cover. Make "every antecedent hit in regression" a sign-off item, and review zero-hit covers like failures. In formal, run the covers too, and treat an unreachable antecedent as a vacuous proof. Track the counts per assertion in the verification plan. Then a property that stops firing after a design change is caught.
Self-Check
Tick each key point you covered in your answer.
Misconception
"The formal tool says proven, so the property is meaningful."
A proof can pass because constraints rule out the antecedent. Without a reached cover, proven may mean vacuous.
Source Seligman, Schubert and Kiran Kumar, Formal Verification (2nd ed.) ch. 9 "Vacuity issues" (PDF p310), Tip 9.11 (p318)
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Break ItWhen Assertions Slow the RegressionL3 Senior
After adding the suite, the regression runs twice as slowly. What do you look for?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Look for properties that keep many attempts alive. Typical causes are level antecedents that start an attempt every cycle, and long or unbounded ranges such as
##[1:$]. Rewrite them with edge antecedents and the spec's bound. Keep the expensive checks in nightly runs if they still cost too much. Measure per property with the simulator's profiler before changing anything.Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Senior)
A good senior answer names the number of open attempts as what drives the cost. It keeps the checks by fixing them, instead of switching them off.
Wrong Altitude
"Turn the assertions off in regression and run them weekly."
Bugs then sit unnoticed for a week. Fix the few expensive properties instead.
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Prove ItSolve 6.6.13: A Tagged Channel Assertion SuiteSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail.
Delivery
Lists assertion counts ("we had 400 assertions") as proof of quality.
A count says nothing about what was checked. The interviewer wants the mapping to spec rules and the cover results.
Wrong Altitude
"We asserted everything we could think of in the RTL."
That checks the implementation against itself. Rules must come from the spec, or a shared misunderstanding passes.
Half-Truth
"Our assertions never fired, so the design was clean."
Silent assertions may never have started. Without antecedent covers, "never fired" can mean "never checked".
Source IEEE 1800-2017 §16.12.7