What a Cover Property Reports in Simulation

Where the interviewer goes next. Open a node to practise that follow-up.

WhyProve ItBreak ItCompareScale It

1. What a Cover Property Reports in Simulation
2. CompareCover Property vs Cover SequenceL2 Mid-Level

   Compare cover property (s) with cover sequence (s) for a sequence with a delay range.

   Reveal the Model Answer

   cover property counts each attempt once, at its first match. cover sequence counts every match, so one attempt of req ##[1:3] ack can add up to three hits. Use cover property to ask "did it happen?", and cover sequence to ask "how many ways did it happen?".

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 cover property counts each attempt once, at its first match. Key point 2 cover sequence counts every match, so one attempt of req ##[1:3] ack can add up to three hits. Key point 3 Use cover property to ask "did it happen?", and cover sequence to ask "how many ways did it happen?".

   Misconception

   "They are two spellings of the same statement."

   They differ in how many successes one attempt can report.

   Source IEEE 1800-2017 §16.14.3

   • Lesson A1.3Implication and Vacuous Success
3. WhyWhy Count Every MatchL2 Mid-Level

   Why would you ever want every match counted?

   Reveal the Model Answer

   Every match is a different timing of the same scenario. Counting them shows whether the tests reached each latency in the window, such as ack after 1, 2 and 3 cycles. A plain yes or no would hide a test that only ever produced one latency.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Every match is a different timing of the same scenario. Key point 2 Counting them shows whether the tests reached each latency in the window, such as ack after 1, 2 and 3 cycles. Key point 3 A plain yes or no would hide a test that only ever produced one latency.

   Half-Truth

   "More hits always mean better coverage."

   Many hits of one timing still leave the other timings untested. What matters is which matches occurred.

   • Lesson A2.1Delays and Ranges: One Attempt, Many Threads
4. Break ItA Match Count That Hides the LatencyL2 Mid-Level

   Break it: the cover of req ##[1:3] ack reports 300 matches. Does that prove the 3-cycle latency was hit?

   Reveal the Model Answer

   No. The count adds up matches of every latency, so all 300 could be latency 1. Write one cover per latency: req ##1 ack, req ##2 ack and req ##3 ack. Or sample the latency into a covergroup with one bin per value.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 No. Key point 2 The count adds up matches of every latency, so all 300 could be latency 1. Key point 3 Write one cover per latency: req ##1 ack, req ##2 ack and req ##3 ack. Key point 4 Or sample the latency into a covergroup with one bin per value.

   Half-Truth

   "A big match count means every latency was exercised."

   The count does not say which latency matched. One latency repeated many times gives the same count.

   • Lesson A2.1Delays and Ranges: One Attempt, Many Threads
5. Prove ItWriting the Cover That Proves an Assertion Checked SomethingL1 JuniorL2 Mid-Level

   Write the cover you would add next to assert property (@(posedge clk) disable iff (rst) req |=> ack);.

   Reveal the Model Answer

   Cover the antecedent with the same clock and reset: cover property (@(posedge clk) disable iff (rst) req);. A nonzero count shows the consequent was checked at least that often. Many teams also cover the whole scenario, req ##1 ack, to show the good path happened.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Cover the antecedent with the same clock and reset: cover property (@(posedge clk) disable iff (rst) req);. Key point 2 A nonzero count shows the consequent was checked at least that often. Key point 3 Many teams also cover the whole scenario, req ##1 ack, to show the good path happened.

   Missed Corner

   Writes the cover without the assertion's disable iff.

   Then it counts req during reset, when the assertion was disabled, and overstates how often the check ran.

   Source IEEE 1800-2017 §16.12 (disable iff); Mehta, SystemVerilog Assertions and Functional Coverage (3rd ed.) §6.8 p102-104

   • Lesson A1.3Implication and Vacuous Success
   • Problem 6.6.6Hold the Offer
6. Prove ItSolve 6.6.6: Hold the OfferSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem 6.6.6

7. Scale ItAssertion Covers in the Coverage PlanL3 Senior

   How do assertion covers fit into the coverage plan for an IP block?

   Reveal the Model Answer

   Each temporal scenario in the plan gets a cover property, next to the covergroups for values. The plan also lists one antecedent cover per important assertion. Coverage closure then needs every cover hit in regression. A cover that stays at zero is reviewed like a failure, because it means a check never ran.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Each temporal scenario in the plan gets a cover property, next to the covergroups for values. Key point 2 The plan also lists one antecedent cover per important assertion. Key point 3 Coverage closure then needs every cover hit in regression. Key point 4 A cover that stays at zero is reviewed like a failure, because it means a check never ran.

   What Interviewers Listen For (Senior)

   A good senior answer makes a cover with zero hits block sign-off. It links each cover to one line of the verification plan.

   Wrong Altitude

   "Covers are for formal; simulation coverage is covergroups."

   Simulators collect cover property results into the same coverage database. Leaving them out loses the temporal half of the plan.

   • Lesson C1What Coverage Measures
   • Lesson A8.1Capstone: An Assertion Suite