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Sequence End Points: Triggered and Matched

L2 Mid-LevelL3 Seniorsvasequencesend points

The Question

The interviewer asks

What do s.triggered and s.matched give you for a named sequence s? When do you need .matched?

Reveal the Model Answer

s.triggered is true at a clock tick where some match of s ends. It does not matter when that match started. So a property can ask "has the whole sequence just finished?" at the moment another signal rises. .matched does the same when s runs on a different clock. It holds the end point until the next tick of the reading clock. Use .triggered within one clock and .matched across clocks.

Done may rise only where the sequence ends
012345abs.triggered (s = a ##1 b)dones ends here, so $rose(done) |-> s.triggered passes

One column per clock tick. A done that rose at tick 1, before b, would fail the rule.

Self-Check

Tick each key point you covered in your answer.

What Interviewers Listen For (Mid-Level)

A good mid-level answer uses .triggered to check that done rises only when the sequence has just ended. It explains why a forward check misses an early done.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfCompareScale It

  1. Sequence End Points: Triggered and Matched
  2. WhyWhy End Points ExistL2 Mid-Level

    Why add end-point methods at all? Can a property not just start from the sequence?

    Reveal the Model Answer

    A property that starts from a sequence looks forward from its end. Some rules look backward instead: "when X happens, Y must have just finished". End points let a property check that backward rule at the moment X happens. They also let you build a sequence out of other sequences' end points.

    Self-Check

    Tick each key point you covered in your answer.

    Half-Truth

    "End points are only syntax sugar."

    They express backward rules that a forward implication cannot, as the early-done case shows.

    Source Mehta, SystemVerilog Assertions and Functional Coverage (3rd ed.), §13.1

  3. What IfWaiting on a Sequence from Testbench CodeL2 Mid-Level

    Asked if they mention testbench code

    What if a test task needs to wait until the bus has finished a full handshake sequence?

    Reveal the Model Answer

    Declare the handshake as a named sequence and write wait (hs.triggered); in the task. The task wakes in the time step where the handshake ends, with no hand-written state machine. .matched cannot be used in a wait; only .triggered can.

    End Points Wake the BlockOne lane per start of the sequence s_ab = a ##2 b. Each pass is an end point, and code that waits on the sequence wakes at each one.a |-> ##2 bMeasured on Verilator 5.052: one copy of the assertion per lane
    attempt startspassfail
    End points wake the blocka @15, from edge 2 (t=15): passes at edge 4 (t=35). a @25, from edge 3 (t=25): passes at edge 5 (t=45). a @65, from edge 7 (t=65): fails at edge 9 (t=85).edgetime15215325435545655765875985clkabattemptsa @15a @15: passes at edge 4 (t=35)a @25a @25: passes at edge 5 (t=45)a @65a @65: fails at edge 9 (t=85)
    1. Edge 2 · t=15

      a at 15 starts a match of a ##2 b.

    2. Edge 3 · t=25

      a again at 25: a second match overlaps the first.

    3. Edge 4 · t=35

      b at 35 completes the first match. always @(s_ab) wakes at 35.

    4. Edge 5 · t=45

      b at 45 completes the second match: another wake-up.

    5. Edge 7 · t=65

      a at 65 starts a third match.

    6. Edge 9 · t=85

      b is low at 85, so this match dies. The lane fails, and the block does not wake.

    Read the lanes as text
    • a @15, from edge 2 (t=15): passes at edge 4 (t=35).
    • a @25, from edge 3 (t=25): passes at edge 5 (t=45).
    • a @65, from edge 7 (t=65): fails at edge 9 (t=85).

    Sampled values, edge 1 to 9: a 0 1 1 0 0 0 1 0 0; b 0 0 0 1 1 0 0 0 0.

    The program behind the lanes

    The lanes come from running this program on Verilator 5.052. Each lane is a separate copy of b_two_later that can start only at that lane's edge, so every verdict and its edge are read from that copy's own output.

    module tb;
      logic clk = 0;
      always #5 clk = ~clk;                 // rising edges at 5, 15, 25, ...
      logic a = 0, b = 0;
      sequence s_ab; @(posedge clk) a ##2 b; endsequence
    
      b_two_later: assert property (@(posedge clk) a |-> ##2 b);
      always @(s_ab) $display("s_ab ended at %0t", $time);
    
      initial begin
        @(negedge clk); a = 1;              // a at 15 and 25
        @(negedge clk);
        @(negedge clk); a = 0; b = 1;       // b at 35 and 45
        @(negedge clk);
        @(negedge clk); b = 0;
        @(negedge clk); a = 1;              // a at 75
        @(negedge clk); a = 0;              // no b at 85
        @(negedge clk);
        @(negedge clk);
        $finish;
      end
    endmodule
    

    Self-Check

    Tick each key point you covered in your answer.

    Half-Truth

    "Use @(hs) and .triggered interchangeably."

    @(hs) waits for the next end point after the wait starts. wait (hs.triggered) also returns if the end point is in the current time step.

    Source IEEE 1800-2017 §9.4.2.4

  4. CompareTriggered vs the Old Ended MethodL2 Mid-Level

    Old code uses s.ended. Compare it with s.triggered.

    Reveal the Model Answer

    They mean the same thing. The 2005 standard used .ended inside sequences and .triggered elsewhere. Later standards allow .triggered everywhere and removed .ended. When you port old code, replace .ended with .triggered.

    Self-Check

    Tick each key point you covered in your answer.

    Misconception

    ".ended waits for the sequence to end; .triggered fires when it starts."

    Both mark the end point of a match. Neither says anything about the start.

    Source Mehta, SystemVerilog Assertions and Functional Coverage (3rd ed.), §13.1

  5. Scale ItBuilding a Protocol Checker from Named SequencesL3 Senior

    How would you structure the assertions for a complex protocol, with many phases, so they stay readable and reusable?

    Reveal the Model Answer

    Write each protocol phase once as a named sequence with arguments, such as address phase, data beat and response. Build properties from those pieces, using end points for "this phase must have just finished" rules. Keep them in a package or a checker that every agent binds. A spec change then touches one sequence, not twenty properties.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Senior)

    A good senior answer treats the sequence library as shared code with an owner and reviews. It notes which pieces the team's tools cannot run, and keeps a fallback for them.

    Wrong Altitude

    "One long property per rule is clearer than shared sequences."

    Long properties repeat the same phases many times. One spec change then needs many edits, and the copies drift.

What People Get Wrong

Common wrong answers and why they fail.

Misconception

"s |=> $rose(done) is the same rule as $rose(done) |-> s.triggered."

The forward rule starts only when s ends. A done that rises early, while s is still running, is never checked. The end-point rule fails at that early rise.

Source Mehta, SystemVerilog Assertions and Functional Coverage (3rd ed.), §13.1

Spec Misquote

".triggered stays true until something reads it."

It is true only in the time step where the match ends. A reader one tick later sees false.

Source IEEE 1800-2017 §16.13.6

Tool as Truth

"Verilator rejects .triggered, so it is not standard SystemVerilog."

It is standard. Verilator 5.052 rejects it at compile time, which is a tool gap.

Source ASIC Point engine notes (Verilator 5.052 SVA probes), rows ".triggered" and ".matched"

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