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Interview Question · Code Writing

Writing Valid Holds Until Ready

L0 FresherL1 Juniorsvahandshakecheckers

The Question

The interviewer asks

Write an assertion for the rule "once valid is high, it must stay high until ready is high". A candidate wrote the line below. Does it check the rule?

systemverilog
assert property (@(posedge clk) valid |-> ##[0:$] ready);
Reveal the Model Answer

No. It only says that some ready comes later, and with no deadline it can never fail in a finite test. It never checks valid in the cycles between. Write the rule cycle by cycle: valid && !ready |=> valid. Every cycle where the offer waits, the next cycle must still show valid.

One cycle of rvalid missing during a stall
01234edge12345rvalidrreadyrdatab2attempt starts: stalled offerhold_valid fails

One column per rising edge; here the signals are rvalid and rready. The rule rvalid && !rready |=> rvalid fails at edge 3, where the offer drops. The data arrives later, so a scoreboard is satisfied.

Self-Check

Tick each key point you covered in your answer.

What Interviewers Listen For (Fresher)

A good fresher answer sees that the candidate's line never looks at valid after the first cycle. It then writes the cycle-by-cycle rule.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItBreak ItCompare

  1. Writing Valid Holds Until Ready
  2. WhyWhy an Open-Ended Wait Cannot FailL1 JuniorL2 Mid-Level

    Why can valid |-> ##[0:$] ready never fail in simulation?

    Reveal the Model Answer

    The window has no end, so there is always a later cycle where ready might still arrive. In an assert, an attempt that is still waiting when the test ends counts as weak, so it does not fail. Only a strong form, such as s_eventually, fails when the test ends first.

    Self-Check

    Tick each key point you covered in your answer.

    Spec Misquote

    "It fails at the end of the test if ready never came."

    A sequence property in an assert is weak by default, so an unfinished attempt is not a failure.

    Source IEEE 1800-2017 §16.12.2

  3. What IfChoosing the Bound for ReadyL1 JuniorL2 Mid-Level

    What if you replace the open window with a bound? What number do you pick, and where does it come from?

    Reveal the Model Answer

    Take it from the spec or the slave's datasheet, such as a maximum number of wait states. If the spec gives none, agree a system timeout with the architect and write it down. Use valid |-> ##[0:N] ready. Then cover the longest legal wait, so tests reach the bound.

    Self-Check

    Tick each key point you covered in your answer.

    Half-Truth

    "Pick N = 1000 so it never fires falsely."

    A huge bound hides a slow slave and reports a hang far from its cause. The bound should come from a spec number.

  4. CompareA Cycle Rule vs Until_with for One HandshakeL1 JuniorL2 Mid-Level

    Compare valid && !ready |=> valid with $rose(valid) |-> valid until_with ready.

    Reveal the Model Answer

    Both catch a withdrawn offer. The cycle rule starts a short attempt on every waiting cycle, so it is easy to read and runs on every tool. The until_with form starts one attempt per offer and follows it to the handshake. It misses offers that start while valid is already high, such as back-to-back beats.

    valid && !ready |=> valid$rose(valid) |-> valid until_with ready
    AttemptsOne per waiting cycleOne per offer
    A withdrawn offerCaughtCaught
    Back-to-back beatsEvery waiting beat is checkedA beat that starts while valid is high gets no attempt

    Self-Check

    Tick each key point you covered in your answer.

    Missed Corner

    "$rose(valid) catches every new offer."

    Back-to-back beats keep valid high, so there is no rise for the second offer. That offer is never checked.

    Source IEEE 1800-2017 §16.9.3

  5. Prove ItSolve 6.6.6: Hold the OfferSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem 6.6.6

  6. Break ItA Hold Rule That Never StartedL1 JuniorL2 Mid-Level

    The hold rule passed across the whole regression. Why might that prove nothing?

    Reveal the Model Answer

    Its antecedent needs a stalled offer. If every test drives ready high, no attempt ever reaches the consequent, and the zero-failure report is vacuous. Count or cover valid && !ready and make a stalling sink part of the agent.

    Self-Check

    Tick each key point you covered in your answer.

    Half-Truth

    "Vacuous passes only come from typos."

    Here the property is correct; the stimulus never creates the situation it checks.

What People Get Wrong

Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.

Misconception

"valid |-> ##[0:$] ready says valid stays high until ready."

The range only waits for a later ready; it says nothing about valid meanwhile. The twin withdraws valid early and the rule reports 0 failures.

Run It

A source that withdraws its offer before ready, checked by the candidate's rule.

RUNVerilator · simulator service
Edit the code, then run it
Expected: failures=0 FAIL: the rule only waits for some later ready; it never checked that valid stayed high
See the Fix
module tb;
  logic clk = 0, valid = 0, ready = 0;
  int fails = 0;
  always #5 clk = ~clk;
  // The fix: once offered and not taken, valid must still be high at the next edge.
  hold_rule: assert property (@(posedge clk) valid && !ready |=> valid) else fails++;
  initial begin
    @(negedge clk) valid = 1;   // offered, not taken
    @(negedge clk) valid = 0;   // withdrawn before ready: illegal
    repeat (3) @(negedge clk);
    @(negedge clk) begin valid = 1; ready = 1; end
    @(negedge clk) begin valid = 0; ready = 0; end
    repeat (2) @(negedge clk);
    $display("failures=%0d", fails);
    if (fails) $display("PASS: the hold rule caught the withdrawn offer");
    $finish;
  end
endmodule

Prints: failures=1 PASS: the hold rule caught the withdrawn offer

Misconception

"Use |-> instead of |=>; it is the same rule."

valid && !ready |-> valid checks the same cycle, where valid is already true. It can never fail.

Source IEEE 1800-2017 §16.12.7

Missed Corner

Writes only the valid rule and forgets the data.

A source can hold valid and still change the data during the stall. The protocol needs both rules.

Source AMBA AXI Protocol Specification IHI 0022L §A2.3 Valid-Ready transport

Learn It, Then Prove It