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Active and Passive Agents

L0 FresherL1 Junioruvmagentreuse

The Question

The interviewer asks

What does this agent build when is_active is UVM_PASSIVE? What is wrong with its connect phase?

systemverilog
function void build_phase(uvm_phase phase);
  mon = bus_monitor::type_id::create("mon", this);
  if (get_is_active() == UVM_ACTIVE) begin
    sqr = bus_sequencer::type_id::create("sqr", this);
    drv = bus_driver::type_id::create("drv", this);
  end
endfunction

function void connect_phase(uvm_phase phase);
  drv.seq_item_port.connect(sqr.seq_item_export);
endfunction
Reveal the Model Answer

A passive agent builds only the monitor; an active agent adds the sequencer and the driver. This connect phase uses drv and sqr even in passive mode, where both are null. So the simulation stops with a null-handle error. Guard the connection with the same get_is_active() test. Use passive agents where the bench only watches, such as an internal bus at SoC level.

What an Agent Package ShipsEverything inside an agent's package except the interface. Arrows are calls or builds; the monitor's arrow is an analysis write.
What an agent package shipsEverything inside an agent's package except the interface. Arrows are calls or builds; the monitor's arrow is an analysis write. sequence API sequences send(x, y, sqr): onecall per transfer object incr_agent_cfg vif, is_active, knobs agent incr_agent Builds the monitor;sqr and drv only whenactive driver incr_driver Items to pins; copies yback into the item monitor incr_monitor Pins to items; oneanalysis port subscriber incr_coverage Subscriber: valuesseen object incr_item x sent, y returned interface incr_if Interface: outsidethe package starts on agent.sqrread in buildbuilds if activebuilds alwayswrite(t)drivessampled
  1. What a test touches

    A test fills the config object and calls API sequences. It never names the driver or the monitor.

    Follow the calls, values and waits
    1. data cfg: UVM_ACTIVE, vif: incr_agent_cfg → incr_agent
  2. Active build

    With UVM_ACTIVE the agent builds a sequencer, a driver and the monitor. The driver is the only class that writes the pins.

    Follow the calls, values and waits
    1. call create mon: incr_agent → incr_monitor
    2. call create sqr, drv: incr_agent → incr_driver
  3. One API call, one transfer

    The test calls send(10, y, sqr). The sequence hands one item to the driver, which drives x=10 and waits for the answer.

    Follow the calls, values and waits
    1. call send(10, y, sqr): API sequences → incr_agent
    2. data x=10: incr_driver → incr_if
    3. Waiting: API sequences — in send(10) until 20 ns
  4. The monitor sees it15 ns (illustrative)

    The monitor samples x=10 and y=11 from the pins and turns them back into an item.

    Follow the calls, values and waits
    1. data x=10, y=11: incr_if → incr_monitor
  5. send returns the answer20 ns (illustrative)

    The driver copies y into the item before item_done, so send returns 11 to the test.

    Follow the calls, values and waits
    1. return returns y=11: incr_agent → API sequences
    2. Released: API sequences
  6. Passive build

    With UVM_PASSIVE only the monitor is built. It still samples the pins and feeds coverage and any checker connected to its port.

    Follow the calls, values and waits
    1. call create mon: incr_agent → incr_monitor
  7. Passive traffic35 ns (illustrative)

    Another block drives port B. The passive monitor samples x=200 and y=201 and publishes the item.

    Follow the calls, values and waits
    1. data x=200, y=201: incr_if → incr_monitor
    2. data write(t): x=200: incr_monitor → incr_coverage
Read the diagram as text
  • API sequences: send(x, y, sqr): one call per transfer
  • incr_agent_cfg: vif, is_active, knobs
  • incr_agent: Builds the monitor; sqr and drv only when active
  • incr_driver: Items to pins; copies y back into the item
  • incr_monitor: Pins to items; one analysis port
  • incr_coverage: Subscriber: values seen
  • incr_item: x sent, y returned
  • incr_if: Interface: outside the package
  • API sequences → incr_agent: starts on agent.sqr
  • incr_agent_cfg → incr_agent: read in build
  • incr_agent → incr_driver: builds if active
  • incr_agent → incr_monitor: builds always
  • incr_monitor → incr_coverage: write(t)
  • incr_driver → incr_if: drives
  • incr_if → incr_monitor: sampled

Seven classes and one interface. The item is shared by the sequences, the driver and the monitor.

Self-Check

Tick each key point you covered in your answer.

What Interviewers Listen For (Fresher)

A good fresher answer says a passive agent builds only the monitor. It spots that the connect phase uses drv even when it is null.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfCompareScale It

  1. Active and Passive Agents
  2. WhyWho Makes an Agent PassiveL1 Junior

    Who decides whether an agent is active, and how?

    Reveal the Model Answer

    Usually the environment or the test, through the configuration database or an agent config object. In uvm-core, uvm_agent reads an is_active setting from the configuration database during its build_phase. get_is_active() returns it, and a subclass may override that function to read its own config object instead.

    Self-Check

    Tick each key point you covered in your answer.

  3. What IfA Passive Agent That Still Builds a DriverL1 JuniorL2 Mid-Level

    What if the agent is set passive, but its build_phase still creates the driver and sequencer?

    Reveal the Model Answer

    The driver then exists, and its run_phase may still drive the bus. At SoC level that fights the real master on the same pins. Call super.build_phase first, then build the driver and sequencer only when get_is_active() returns UVM_ACTIVE. Guard their connection with the same test.

    Self-Check

    Tick each key point you covered in your answer.

    Misconception

    "Passive just means no sequences are started."

    A driver that exists still runs its loop and can drive idle values onto the pins. Passive must mean the driver is never built.

    Source Lesson U11.1 key points

  4. CompareA Passive Agent vs a Bare MonitorL1 JuniorL2 Mid-Level

    Compare a passive agent with simply instantiating the monitor on its own.

    Reveal the Model Answer

    The passive agent keeps the same structure, config object and analysis port as the active one. Scoreboards and coverage connect to it the same way at every level. A bare monitor works too, but each environment then wires it differently. The agent is the unit you reuse.

    Self-Check

    Tick each key point you covered in your answer.

  5. Scale ItWhich Agents Turn Passive at SoC LevelL2 Mid-LevelL3 Senior

    Scale it: at SoC level, which of your block agents become passive?

    Reveal the Model Answer

    Any agent whose interface is now driven by real RTL turns passive, such as the block's internal bus. Agents on the chip boundary stay active, because the bench still drives those pins. The passive agents keep feeding their scoreboards and coverage, so the block checks keep running inside the chip.

    Self-Check

    Tick each key point you covered in your answer.

    Wrong Altitude

    "Drop the block agents at SoC level; the system tests cover it."

    System tests reach block corners rarely. The block's passive monitors and checkers find bugs there for almost no cost.

  6. What IfIs a Responding Slave Agent Active?L2 Mid-Level

    What if the agent models a memory slave that answers the DUT? Is it active or passive?

    Reveal the Model Answer

    Active, even though the DUT starts every transfer. The agent drives the response pins, so it needs a driver and usually a sequence that produces the responses. Passive means the agent drives nothing at all.

    Self-Check

    Tick each key point you covered in your answer.

What People Get Wrong

Common wrong answers and why they fail.

Missed Corner

"The connect phase does not need the is_active check; it only connects ports."

In passive mode drv and sqr were never created. Calling connect through a null handle is a fatal error at run time.

Source Accellera, UVM 1.1 User's Guide, §3.8.1 operating modes: passive mode builds no driver or sequencer (PDF p52)

Misconception

"A passive agent still drives the bus, with idle values."

A passive agent has no driver, so it drives nothing. Another master, or the real RTL, owns those pins.

Source Accellera, UVM 1.1 User's Guide, §3.8.1 operating modes (PDF p52)

Half-Truth

"Make an agent passive by not starting any sequence on it."

The driver still exists and usually drives its idle values onto pins that real RTL also drives. At SoC level that causes contention.

Learn It, Then Prove It