Interview Question · Code Reading

A Scoreboard Across a Mid-Test Reset

L2 Mid-Leveluvmresetscoreboard

The interviewer asks

A test asserts reset while a result is inside the DUT, then sends more traffic. This scoreboard ignores reset. What does it report?

systemverilog

function void write_out(incr_result r);
  bit [7:0] want;
  if (r.reset) return;   // reset is the design's business
  if (expected.size() == 0) begin
    `uvm_error("SB", $sformatf("y=%0d with no input waiting", r.y))
    return;
  end
  want = expected.pop_front();
  checked++;
  if (r.y != want) begin
    mismatches++;
    `uvm_error("SB", $sformatf("y=%0d, expected %0d", r.y, want))
  end
endfunction

Reveal the Model Answer

It reports a false mismatch. Reset destroyed the result for input 32, but its prediction, 33, stays at the front of the queue. The first result after reset, 81, is compared with 33. Then the prediction 81 waits forever, and the end check reports it missing. The scoreboard must treat reset as an event: count its open predictions as canceled and empty the queue.

What the queue holds through reset

The prediction outlives the result it predicted.

Self-Check

Tick each key point you covered in your answer.

Key point 1 It reports a false mismatch. Key point 2 Reset destroyed the result for input 32, but its prediction, 33, stays at the front of the queue. Key point 3 The first result after reset, 81, is compared with 33. Key point 4 Then the prediction 81 waits forever, and the end check reports it missing. Key point 5 The scoreboard must treat reset as an event: count its open predictions as canceled and empty the queue.

What Interviewers Listen For (Mid-Level)

A good mid-level answer traces the queue through the reset. It predicts both errors: the false mismatch and the prediction left at the end.

What People Get Wrong

Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.

Misconception

"Reset is the design's business; the scoreboard does not need to know."

The design drops what it held, but the scoreboard still expects it. The twin compares the first result after reset with a prediction from before it.

Run It

The lesson U10.2 bench with a scoreboard that ignores reset.

RUNVerilator + UVM 2020.3.1 · simulator service

Edit the code, then run it

Expected among the UVM messages: 35 ns scoreboard y=17 checked 50 ns test reset on 55 ns driver reset: drops x=48, no item_done 70 ns test reset off checked 2, mismatches 1, still waiting 1 FAIL: the scoreboard kept the prediction for a result that reset destroyed

`timescale 1ns/1ns
`include "uvm_macros.svh"
import uvm_pkg::*;

// The incrementer from U7 with a reset. It captures x at edge k (valid and ready both 1), is busy
// for two edges, and drives y = x + 1 with out_valid after edge k+1; monitors see it at edge k+2.
// Reset clears the busy count and drops a result still inside. STUCK_AFTER > 0 makes ready stay
// low for good after that many accepts (a hung design).
interface incr_if (input logic clk);
  logic       rst = 0;
  logic       valid = 0;
  logic [7:0] x = 0;
  logic       ready;
  logic       out_valid = 0;
  logic [7:0] y = 0;
endinterface

module incr_pipe #(parameter int STUCK_AFTER = 0) (incr_if bus);
  logic [1:0] busy = 0;
  logic       staged = 0;
  logic [7:0] stage = 0;
  int         taken = 0;
  assign bus.ready = (busy == 0) && !bus.rst && !(STUCK_AFTER > 0 && taken >= STUCK_AFTER);
  always @(posedge bus.clk) begin
    bus.out_valid <= staged && !bus.rst;
    bus.y         <= stage;
    staged        <= bus.valid && bus.ready;
    stage         <= bus.x + 1;
    if (bus.rst)                     busy <= 0;
    else if (bus.valid && bus.ready) begin busy <= 2; taken <= taken + 1; end
    else if (busy != 0)              busy <= busy - 1;
  end
endmodule

function automatic void log_event(string who, string what);
  $display("%3d ns  %-11s%s", $time, who, what);
endfunction

class incr_item extends uvm_sequence_item;
  `uvm_object_utils(incr_item)
  bit [7:0] x;
  function new(string name = "incr_item"); super.new(name); endfunction
endclass

// What the monitor sees coming out; reset = 1 marks an edge with reset held.
class incr_result extends uvm_sequence_item;
  `uvm_object_utils(incr_result)
  bit [7:0] y;
  bit       reset;
  function new(string name = "incr_result"); super.new(name); endfunction
endclass

// Sends the values in the queue, one item each.
class incr_seq extends uvm_sequence #(incr_item);
  `uvm_object_utils(incr_seq)
  bit [7:0] values[$];
  string    lane = "";
  function new(string name = "incr_seq"); super.new(name); values = '{16, 32, 48}; endfunction
  task body();
    foreach (values[i]) begin
      incr_item it = incr_item::type_id::create("it");
      start_item(it);
      it.x = values[i];
      finish_item(it);
    end
  endtask
endclass

class incr_driver extends uvm_driver #(incr_item);
  `uvm_component_utils(incr_driver)
  virtual incr_if vif;
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
  task run_phase(uvm_phase phase);
    forever begin
      @(negedge vif.clk);
      if (vif.rst) begin                     // no new item while reset is held
        vif.valid <= 0;
        continue;
      end
      seq_item_port.try_next_item(req);
      if (req == null) begin
        vif.valid <= 0;
        continue;
      end
      vif.valid <= 1;
      vif.x     <= req.x;
      do @(posedge vif.clk); while (!vif.ready && !vif.rst);
      if (vif.rst) begin                     // reset: the sequencer has forgotten this item
        vif.valid <= 0;
        log_event("driver", $sformatf("reset: drops x=%0d, no item_done", req.x));
        continue;
      end
      seq_item_port.item_done();
    end
  endtask
endclass

class incr_monitor extends uvm_monitor;
  `uvm_component_utils(incr_monitor)
  virtual incr_if vif;
  uvm_analysis_port #(incr_item)   in_ap;
  uvm_analysis_port #(incr_result) out_ap;
  function new(string name, uvm_component parent);
    super.new(name, parent);
    in_ap  = new("in_ap", this);
    out_ap = new("out_ap", this);
  endfunction
  task run_phase(uvm_phase phase);
    forever begin
      @(posedge vif.clk);
      if (vif.rst) begin                       // reset is part of what happened
        incr_result r = incr_result::type_id::create("r");
        r.reset = 1;
        out_ap.write(r);
        continue;
      end
      if (vif.valid && vif.ready) begin
        incr_item t = incr_item::type_id::create("t");
        t.x = vif.x;
        in_ap.write(t);
      end
      if (vif.out_valid) begin
        incr_result r = incr_result::type_id::create("r");
        r.y = vif.y;
        out_ap.write(r);
      end
    end
  endtask
endclass

`uvm_analysis_imp_decl(_in)
`uvm_analysis_imp_decl(_out)

class incr_scoreboard extends uvm_component;
  `uvm_component_utils(incr_scoreboard)
  uvm_analysis_imp_in  #(incr_item, incr_scoreboard)   in_imp;
  uvm_analysis_imp_out #(incr_result, incr_scoreboard) out_imp;
  bit [7:0] expected[$];
  int inputs, checked, canceled, mismatches;
  function new(string name, uvm_component parent);
    super.new(name, parent);
    in_imp  = new("in_imp", this);
    out_imp = new("out_imp", this);
  endfunction
  function void write_in(incr_item t);
    inputs++;
    expected.push_back(t.x + 1);
  endfunction
  function void write_out(incr_result r);
    bit [7:0] want;
    if (r.reset) return;   // the belief: reset is the design's business, not the scoreboard's
    if (expected.size() == 0) begin
      `uvm_error("SB", $sformatf("result y=%0d with no input waiting", r.y))
      return;
    end
    want = expected.pop_front();
    checked++;
    if (r.y != want) begin
      mismatches++;
      `uvm_error("SB", $sformatf("y=%0d, expected %0d", r.y, want))
    end
    else log_event("scoreboard", $sformatf("y=%0d checked", r.y));
  endfunction
  function void check_phase(uvm_phase phase);
    if (expected.size() != 0)
      `uvm_error("SB", $sformatf("%0d expected results never arrived", expected.size()))
  endfunction
endclass

class reset_test extends uvm_test;
  `uvm_component_utils(reset_test)
  uvm_sequencer #(incr_item) sqr;
  incr_driver     drv;
  incr_monitor    mon;
  incr_scoreboard sb;
  virtual incr_if vif;
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
  function void build_phase(uvm_phase phase);
    sqr = uvm_sequencer #(incr_item)::type_id::create("sqr", this);
    drv = incr_driver::type_id::create("drv", this);
    mon = incr_monitor::type_id::create("mon", this);
    sb  = incr_scoreboard::type_id::create("sb", this);
    if (!uvm_config_db #(virtual incr_if)::get(this, "", "vif", vif))
      `uvm_fatal("NOVIF", "no virtual interface")
    drv.vif = vif;
    mon.vif = vif;
  endfunction
  function void connect_phase(uvm_phase phase);
    drv.seq_item_port.connect(sqr.seq_item_export);
    mon.in_ap.connect(sb.in_imp);
    mon.out_ap.connect(sb.out_imp);
  endfunction
  task run_phase(uvm_phase phase);
    incr_seq first  = incr_seq::type_id::create("first");
    incr_seq second = incr_seq::type_id::create("second");
    second.values = '{80};
    phase.raise_objection(this);
    fork first.start(sqr); join_none
    repeat (5) @(negedge vif.clk);
    vif.rst <= 1;                            // reset in the middle of traffic
    log_event("test", "reset on");
    @(posedge vif.clk);
    sqr.stop_sequences();                    // kill the sequences, flush the sequencer
    repeat (2) @(negedge vif.clk);
    vif.rst <= 0;
    log_event("test", "reset off");
    second.start(sqr);                       // fresh traffic after reset
    fork
      wait (sb.expected.size() == 0);
      #300;                                  // give up: a result is still owed
    join_any
    phase.drop_objection(this);
  endtask
  function void report_phase(uvm_phase phase);
    $display("checked %0d, mismatches %0d, still waiting %0d", sb.checked, sb.mismatches, sb.expected.size());
    if (sb.mismatches != 0)
      $display("FAIL: the scoreboard kept the prediction for a result that reset destroyed");
  endfunction
endclass

module tb;
  bit clk;
  always #5 clk = ~clk;
  incr_if bus (clk);
  incr_pipe dut (bus);
  initial begin
      uvm_config_db #(virtual incr_if)::set(null, "uvm_test_top", "vif", bus);
    run_test("reset_test");
  end
endmodule

See the Fix

`timescale 1ns/1ns
`include "uvm_macros.svh"
import uvm_pkg::*;

// The incrementer from U7 with a reset. It captures x at edge k (valid and ready both 1), is busy
// for two edges, and drives y = x + 1 with out_valid after edge k+1; monitors see it at edge k+2.
// Reset clears the busy count and drops a result still inside. STUCK_AFTER > 0 makes ready stay
// low for good after that many accepts (a hung design).
interface incr_if (input logic clk);
  logic       rst = 0;
  logic       valid = 0;
  logic [7:0] x = 0;
  logic       ready;
  logic       out_valid = 0;
  logic [7:0] y = 0;
endinterface

module incr_pipe #(parameter int STUCK_AFTER = 0) (incr_if bus);
  logic [1:0] busy = 0;
  logic       staged = 0;
  logic [7:0] stage = 0;
  int         taken = 0;
  assign bus.ready = (busy == 0) && !bus.rst && !(STUCK_AFTER > 0 && taken >= STUCK_AFTER);
  always @(posedge bus.clk) begin
    bus.out_valid <= staged && !bus.rst;
    bus.y         <= stage;
    staged        <= bus.valid && bus.ready;
    stage         <= bus.x + 1;
    if (bus.rst)                     busy <= 0;
    else if (bus.valid && bus.ready) begin busy <= 2; taken <= taken + 1; end
    else if (busy != 0)              busy <= busy - 1;
  end
endmodule

function automatic void log_event(string who, string what);
  $display("%3d ns  %-11s%s", $time, who, what);
endfunction

class incr_item extends uvm_sequence_item;
  `uvm_object_utils(incr_item)
  bit [7:0] x;
  function new(string name = "incr_item"); super.new(name); endfunction
endclass

// What the monitor sees coming out; reset = 1 marks an edge with reset held.
class incr_result extends uvm_sequence_item;
  `uvm_object_utils(incr_result)
  bit [7:0] y;
  bit       reset;
  function new(string name = "incr_result"); super.new(name); endfunction
endclass

// Sends the values in the queue, one item each.
class incr_seq extends uvm_sequence #(incr_item);
  `uvm_object_utils(incr_seq)
  bit [7:0] values[$];
  string    lane = "";
  function new(string name = "incr_seq"); super.new(name); values = '{16, 32, 48}; endfunction
  task body();
    foreach (values[i]) begin
      incr_item it = incr_item::type_id::create("it");
      start_item(it);
      it.x = values[i];
      finish_item(it);
    end
  endtask
endclass

class incr_driver extends uvm_driver #(incr_item);
  `uvm_component_utils(incr_driver)
  virtual incr_if vif;
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
  task run_phase(uvm_phase phase);
    forever begin
      @(negedge vif.clk);
      if (vif.rst) begin                     // no new item while reset is held
        vif.valid <= 0;
        continue;
      end
      seq_item_port.try_next_item(req);
      if (req == null) begin
        vif.valid <= 0;
        continue;
      end
      vif.valid <= 1;
      vif.x     <= req.x;
      do @(posedge vif.clk); while (!vif.ready && !vif.rst);
      if (vif.rst) begin                     // reset: the sequencer has forgotten this item
        vif.valid <= 0;
        log_event("driver", $sformatf("reset: drops x=%0d, no item_done", req.x));
        continue;
      end
      seq_item_port.item_done();
    end
  endtask
endclass

class incr_monitor extends uvm_monitor;
  `uvm_component_utils(incr_monitor)
  virtual incr_if vif;
  uvm_analysis_port #(incr_item)   in_ap;
  uvm_analysis_port #(incr_result) out_ap;
  function new(string name, uvm_component parent);
    super.new(name, parent);
    in_ap  = new("in_ap", this);
    out_ap = new("out_ap", this);
  endfunction
  task run_phase(uvm_phase phase);
    forever begin
      @(posedge vif.clk);
      if (vif.rst) begin                       // reset is part of what happened
        incr_result r = incr_result::type_id::create("r");
        r.reset = 1;
        out_ap.write(r);
        continue;
      end
      if (vif.valid && vif.ready) begin
        incr_item t = incr_item::type_id::create("t");
        t.x = vif.x;
        in_ap.write(t);
      end
      if (vif.out_valid) begin
        incr_result r = incr_result::type_id::create("r");
        r.y = vif.y;
        out_ap.write(r);
      end
    end
  endtask
endclass

`uvm_analysis_imp_decl(_in)
`uvm_analysis_imp_decl(_out)

class incr_scoreboard extends uvm_component;
  `uvm_component_utils(incr_scoreboard)
  uvm_analysis_imp_in  #(incr_item, incr_scoreboard)   in_imp;
  uvm_analysis_imp_out #(incr_result, incr_scoreboard) out_imp;
  bit [7:0] expected[$];
  int inputs, checked, canceled, mismatches;
  function new(string name, uvm_component parent);
    super.new(name, parent);
    in_imp  = new("in_imp", this);
    out_imp = new("out_imp", this);
  endfunction
  function void write_in(incr_item t);
    inputs++;
    expected.push_back(t.x + 1);
  endfunction
  function void write_out(incr_result r);
    bit [7:0] want;
    if (r.reset) begin     // the fix: the design dropped these results, so drop the predictions
      canceled += expected.size();
      expected.delete();
      return;
    end
    if (expected.size() == 0) begin
      `uvm_error("SB", $sformatf("result y=%0d with no input waiting", r.y))
      return;
    end
    want = expected.pop_front();
    checked++;
    if (r.y != want) begin
      mismatches++;
      `uvm_error("SB", $sformatf("y=%0d, expected %0d", r.y, want))
    end
    else log_event("scoreboard", $sformatf("y=%0d checked", r.y));
  endfunction
  function void check_phase(uvm_phase phase);
    if (expected.size() != 0)
      `uvm_error("SB", $sformatf("%0d expected results never arrived", expected.size()))
  endfunction
endclass

class reset_test extends uvm_test;
  `uvm_component_utils(reset_test)
  uvm_sequencer #(incr_item) sqr;
  incr_driver     drv;
  incr_monitor    mon;
  incr_scoreboard sb;
  virtual incr_if vif;
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
  function void build_phase(uvm_phase phase);
    sqr = uvm_sequencer #(incr_item)::type_id::create("sqr", this);
    drv = incr_driver::type_id::create("drv", this);
    mon = incr_monitor::type_id::create("mon", this);
    sb  = incr_scoreboard::type_id::create("sb", this);
    if (!uvm_config_db #(virtual incr_if)::get(this, "", "vif", vif))
      `uvm_fatal("NOVIF", "no virtual interface")
    drv.vif = vif;
    mon.vif = vif;
  endfunction
  function void connect_phase(uvm_phase phase);
    drv.seq_item_port.connect(sqr.seq_item_export);
    mon.in_ap.connect(sb.in_imp);
    mon.out_ap.connect(sb.out_imp);
  endfunction
  task run_phase(uvm_phase phase);
    incr_seq first  = incr_seq::type_id::create("first");
    incr_seq second = incr_seq::type_id::create("second");
    second.values = '{80};
    phase.raise_objection(this);
    fork first.start(sqr); join_none
    repeat (5) @(negedge vif.clk);
    vif.rst <= 1;                            // reset in the middle of traffic
    log_event("test", "reset on");
    @(posedge vif.clk);
    sqr.stop_sequences();                    // kill the sequences, flush the sequencer
    repeat (2) @(negedge vif.clk);
    vif.rst <= 0;
    log_event("test", "reset off");
    second.start(sqr);                       // fresh traffic after reset
    fork
      wait (sb.expected.size() == 0);
      #300;                                  // give up: a result is still owed
    join_any
    phase.drop_objection(this);
  endtask
  function void report_phase(uvm_phase phase);
    $display("checked %0d, mismatches %0d, still waiting %0d", sb.checked, sb.mismatches, sb.expected.size());
    if (sb.mismatches == 0 && sb.expected.size() == 0)
      $display("PASS: reset canceled %0d prediction, and the result after reset matched", sb.canceled);
  endfunction
endclass

module tb;
  bit clk;
  always #5 clk = ~clk;
  incr_if bus (clk);
  incr_pipe dut (bus);
  initial begin
      uvm_config_db #(virtual incr_if)::set(null, "uvm_test_top", "vif", bus);
    run_test("reset_test");
  end
endmodule

Prints: 70 ns test reset off 105 ns scoreboard y=81 checked checked 2, mismatches 0, still waiting 0 PASS: reset canceled 1 prediction, and the result after reset matched UVM_ERROR : 0

Missed Corner

"Kill the sequences on reset and you are done."

Killing sequences stops new stimulus only. The driver may still hold an item, and the scoreboard still holds predictions. Each needs its own reset path.

Source Lesson U10.2 example: the driver drops x=48 and the scoreboard cancels one prediction

Half-Truth

"UVM has a reset phase, so a mid-test reset is handled for you."

reset_phase runs once, before the main phases. A reset during run_phase needs your own handling, or a phase jump that every component must support.

Find Your Next Track

Put Your Skills to Work

Prepare to Explain Your Thinking

An Idea to Try? Pick a Tool.

A Scoreboard Across a Mid-Test Reset

Your Answer

Self-Check

What Interviewers Listen For (Mid-Level)

What Interviewers Listen For (Senior)

Cross-Questions

Your Answer

Self-Check

Your Answer

Self-Check

Your Answer

Self-Check

What Interviewers Listen For (Senior)

Your Answer

Self-Check

Your Answer

Self-Check

What Interviewers Listen For (Staff)

What People Get Wrong

Learn It, Then Prove It

The Question

Your Answer

Self-Check

What Interviewers Listen For (Mid-Level)

What Interviewers Listen For (Senior)

Cross-Questions

Your Answer

Self-Check

Your Answer

Self-Check

Your Answer

Self-Check

What Interviewers Listen For (Senior)

Your Answer

Self-Check

Your Answer

Self-Check

What Interviewers Listen For (Staff)

What People Get Wrong

Learn It, Then Prove It