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Interview Question · Debug
A Test That Passed in Zero Time
The Question
The interviewer asks
A new test that sends 200 items has passed in every regression. A reviewer opens its log, shown below. What went wrong?
UVM_INFO @ 0: reporter [RNTST] Running test incr_test...
check_phase at 0 ns: sent=0 checked=0
UVM_INFO uvm/base/uvm_report_server.svh(1009) @ 0: reporter [UVM/REPORT/SERVER]
--- UVM Report Summary ---
UVM_INFO : 2
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
The whole test ran at time 0, and nothing was sent or checked. No component raised an objection, so the run phase ended in its first time step. UVM then killed the sequence before its first item. Starting a sequence does not keep the phase open. The test must raise an objection before seq.start() and drop it afterwards.
Nobody raised an objection, so the run phase ended at 0 ns. The items planned for 10, 20 and 30 ns were never sent.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer reads "@ 0" and "sent=0" in the log before naming objections. Then it writes the raise and the drop around the sequence.
What Interviewers Listen For (Mid-Level)
A good mid-level answer also adds a check that fails any test that checked nothing. Then a zero-time pass can never look green again.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItBreak ItCompare
- A Test That Passed in Zero Time
-
WhyWhy the Run Phase Ends at Time 0L1 Junior
Why does the phase end at exactly time 0, and not when the sequence finishes?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
The run phase ends when its objection count reaches zero, and the count starts at zero. After the run tasks start, the phase sees nobody objecting and ends in the same time step. It then kills every run task that is still running, including the sequence.
Phase timeline of a test that objects for 30 ns eoe is end_of_elaboration and sos is start_of_simulation. The objection count goes 0, 1, 0, and the run phase ends when it drops back to 0 at 30 ns. Function phases take no time.
Self-Check
Tick each key point you covered in your answer.
Misconception
"UVM waits for every
run_phasetask to return."Drivers and monitors loop forever, so waiting for them would never end. The phase is ended by objections, and leftover tasks are killed.
Source Verification Academy, UVM Cookbook, End Of Test Mechanisms (PDF p190)
-
Break ItDropping the Objection When Start ReturnsL1 JuniorL2 Mid-Level
Break it: the test raises, starts the sequence, and drops when
start()returns. When can that still end too early?2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
start()returns when the sequence body ends, after the lastitem_done(). The last transaction may still be inside the DUT, with its result not yet checked. Dropping then ends the phase and kills the scoreboard's wait. Add a drain time, or let the scoreboard object until its queue is empty.Self-Check
Tick each key point you covered in your answer.
Missed Corner
"When the sequence returns, all traffic is done."
It means the driver finished the last item. The DUT and the scoreboard can still be working on it.
Source Verification Academy, UVM Cookbook, End Of Test Mechanisms (PDF p190-191)
-
CompareObjecting in the Test or the SequenceL2 Mid-Level
Compare raising the objection in the test with letting the sequence object for itself.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
A test-level objection is simple and visible: the test knows what it started. A sequence can object for itself with
set_automatic_phase_objection(1), which raises before its body and drops after. That suits default sequences started without a test task. Pick one owner, so the count is easy to read when you trace it.Self-Check
Tick each key point you covered in your answer.
Spec Misquote
"Use
starting_phase.raise_objection()in the sequence."That is UVM 1.1 style. IEEE 1800.2 replaced it with
get_starting_phase()and the automatic objection.Source uvm-core 2020.3.1 (IEEE 1800.2 library) source, seq/uvm_sequence_base.svh, set_automatic_phase_objection (IEEE 1800.2-2020 §14.2.4.4)
-
Prove ItSolve U5.3.1: A Background Sequence That Leaves Cleanly When KilledSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
-
What IfEnding a Test After a Fixed DelayL1 Junior
Asked if they suggest a long delay instead
What if someone fixes the test by adding
#10usat the end ofrun_phase, inside an objection?2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
It passes today and breaks later. If the sequence grows or the DUT slows, the delay ends the test too early. If the work is short, every run wastes the extra time. Tie the end to the work: drop the objection when the sequence returns, and cover in-flight results separately.
Self-Check
Tick each key point you covered in your answer.
Half-Truth
"A long delay is the safe choice."
Too long wastes regression time on every seed. Too short silently skips results. Neither tracks the real work.
Source Verification Academy, UVM Cookbook, End Of Test Mechanisms (PDF p190)
-
Break ItAn Objection That Never DropsL2 Mid-Level
How does the opposite failure look: an objection that is raised and never dropped?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
The run phase never ends, so the test hangs until UVM's global timeout of 9200 seconds of simulated time. With a running clock, that can take hours. Set a timeout that fits the test with
uvm_root::get().set_timeout(), and trace objections to see who still holds one.Start from How the Run EndedArrows lead from an observation to the next thing to look at. The middle column is the symptom, with its usual cause; the right column is the first tool to run. Illustrative sequenceCallValueReturnWaiting- Ended at 0 ns
Nothing held the run phase open, so it ended before the first clock edge. The objection trace shows no
run_objectionraised by the test.Follow the calls, values and waits
- data run ended at 0 ns: Read the last lines → Ended at 0 ns
- data run ended at 0 ns: Ended at 0 ns → +UVM_OBJECTION_TRACE
- Stopped by the timeout
Something raised an objection and is still waiting. With phase tracing on, the timeout prints the outstanding objections by component; then ask what that component is waiting for.
Follow the calls, values and waits
- data PH_TIMEOUT fatal: Read the last lines → Stopped by the timeout
- data PH_TIMEOUT fatal: Stopped by the timeout → +UVM_TIMEOUT, +UVM_PHASE_TRACE
- Ended on time, numbers wrong
The run completed, so look at the ledger. Each short count names the boundary to inspect: items requested vs sent, errors asked for vs injected, beats sent vs checked.
Follow the calls, values and waits
- data requested 8, driver sent 4: Read the last lines → Ended on time, ledger short
- data requested 8, driver sent 4: Ended on time, ledger short → Config, factory, port tools
Read the diagram as text
- Read the last lines: End time, summary counts, ledger
- Ended at 0 ns: No run_phase objection was raised
- Stopped by the timeout: An objection was never dropped
- Ended on time, ledger short: Work was lost between two parts
- +UVM_OBJECTION_TRACE: No run_objection raised line
- +UVM_TIMEOUT, +UVM_PHASE_TRACE: Lists who still holds an objection
- Config, factory, port tools: Chosen by which ledger line is short
- Read the last lines → Ended at 0 ns: time 0
- Read the last lines → Stopped by the timeout: PH_TIMEOUT fatal
- Read the last lines → Ended on time, ledger short: normal end
- Ended at 0 ns → +UVM_OBJECTION_TRACE: confirm
- Stopped by the timeout → +UVM_TIMEOUT, +UVM_PHASE_TRACE: find the holder
- Ended on time, ledger short → Config, factory, port tools: follow the line
The way a run ends narrows the cause before any trace is switched on.
Self-Check
Tick each key point you covered in your answer.
Missed Corner
"The simulator will stop it when nothing is happening."
A free-running clock is always happening. Only an objection drop or the UVM timeout ends the phase.
Source uvm-core 2020.3.1 (IEEE 1800.2 library) source, macros/uvm_global_defines.svh, `UVM_DEFAULT_TIMEOUT 9200s
- Ended at 0 ns
-
Prove ItSolve 7.7.3: Premature Test CompletionSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Misconception
"A running sequence keeps the test alive until it finishes."
The phase looks only at the objection count. With nothing raised, it ends at time 0 and kills the sequence.
Run It
The interview's test: it starts a three-item sequence and raises nothing.
check_phase at 0 ns: sent=0 checked=0 FAIL: nothing raised an objection, so the run phase ended at time 0 and killed the sequenceSee the Fix
`timescale 1ns/1ns
`include "uvm_macros.svh"
import uvm_pkg::*;
interface incr_if (input logic clk);
logic in_valid = 0, out_valid;
logic [7:0] x = 0, y;
endinterface
module incr_pipe (incr_if bus);
logic v[3]; logic [7:0] d[3];
always_ff @(posedge bus.clk) begin
v[0] <= bus.in_valid; d[0] <= bus.x + 1;
v[1] <= v[0]; d[1] <= d[0];
v[2] <= v[1]; d[2] <= d[1];
end
assign bus.out_valid = v[2];
assign bus.y = d[2];
endmodule
class incr_item extends uvm_sequence_item;
`uvm_object_utils(incr_item)
bit [7:0] x, y;
function new(string name = "incr_item"); super.new(name); endfunction
endclass
class three_items extends uvm_sequence #(incr_item);
`uvm_object_utils(three_items)
function new(string name = "three_items"); super.new(name); endfunction
task body();
for (int i = 1; i <= 3; i++) begin
req = incr_item::type_id::create("req");
start_item(req);
req.x = 8'(10 * i);
finish_item(req);
end
endtask
endclass
class incr_driver extends uvm_driver #(incr_item);
`uvm_component_utils(incr_driver)
virtual incr_if vif;
function new(string name, uvm_component parent); super.new(name, parent); endfunction
task run_phase(uvm_phase phase);
forever begin
seq_item_port.get_next_item(req);
@(negedge vif.clk) begin vif.in_valid <= 1; vif.x <= req.x; end
@(negedge vif.clk) vif.in_valid <= 0;
seq_item_port.item_done();
end
endtask
endclass
class incr_monitor extends uvm_monitor;
`uvm_component_utils(incr_monitor)
virtual incr_if vif;
uvm_analysis_port #(incr_item) in_ap, out_ap;
function new(string name, uvm_component parent); super.new(name, parent); endfunction
function void build_phase(uvm_phase phase); in_ap = new("in_ap", this); out_ap = new("out_ap", this); endfunction
task run_phase(uvm_phase phase);
forever begin
@(posedge vif.clk);
if (vif.in_valid) begin incr_item t = incr_item::type_id::create("in"); t.x = vif.x; in_ap.write(t); end
if (vif.out_valid) begin incr_item t = incr_item::type_id::create("out"); t.y = vif.y; out_ap.write(t); end
end
endtask
endclass
`uvm_analysis_imp_decl(_in)
`uvm_analysis_imp_decl(_out)
class incr_scoreboard extends uvm_scoreboard;
`uvm_component_utils(incr_scoreboard)
uvm_analysis_imp_in #(incr_item, incr_scoreboard) in_imp;
uvm_analysis_imp_out #(incr_item, incr_scoreboard) out_imp;
bit [7:0] expected[$];
int sent, checked;
function new(string name, uvm_component parent); super.new(name, parent); endfunction
function void build_phase(uvm_phase phase); in_imp = new("in_imp", this); out_imp = new("out_imp", this); endfunction
function void write_in(incr_item t); expected.push_back(t.x + 1); sent++; endfunction
function void write_out(incr_item t);
bit [7:0] want = expected.pop_front();
checked++;
if (t.y !== want) `uvm_error("MISMATCH", $sformatf("y=%0d, expected %0d", t.y, want))
endfunction
endclass
class incr_env extends uvm_env;
`uvm_component_utils(incr_env)
uvm_sequencer #(incr_item) sqr;
incr_driver drv; incr_monitor mon; incr_scoreboard sb;
function new(string name, uvm_component parent); super.new(name, parent); endfunction
function void build_phase(uvm_phase phase);
virtual incr_if vif;
if (!uvm_config_db #(virtual incr_if)::get(this, "", "vif", vif)) `uvm_fatal("NOVIF", "no virtual interface")
sqr = uvm_sequencer #(incr_item)::type_id::create("sqr", this);
drv = incr_driver::type_id::create("drv", this);
mon = incr_monitor::type_id::create("mon", this);
sb = incr_scoreboard::type_id::create("sb", this);
drv.vif = vif; mon.vif = vif;
endfunction
function void connect_phase(uvm_phase phase);
drv.seq_item_port.connect(sqr.seq_item_export);
mon.in_ap.connect(sb.in_imp);
mon.out_ap.connect(sb.out_imp);
endfunction
endclass
class incr_test extends uvm_test;
`uvm_component_utils(incr_test)
incr_env env;
function new(string name, uvm_component parent); super.new(name, parent); endfunction
function void build_phase(uvm_phase phase); env = incr_env::type_id::create("env", this); endfunction
task run_phase(uvm_phase phase);
three_items seq = three_items::type_id::create("seq");
phase.get_objection().set_drain_time(this, 50ns); // let the last results come out
phase.raise_objection(this, "three items");
seq.start(env.sqr);
phase.drop_objection(this, "sequence done");
endtask
function void check_phase(uvm_phase phase);
$display("check_phase at %0t ns: sent=%0d checked=%0d", $time, env.sb.sent, env.sb.checked);
if (env.sb.checked == 0) $display("FAIL: nothing raised an objection, so the run phase ended at time 0 and killed the sequence");
else $display("PASS: the objection kept the run phase open");
endfunction
endclass
module tb;
bit clk;
always #5 clk = ~clk;
incr_if bus (clk);
incr_pipe dut (bus);
initial begin
uvm_config_db #(virtual incr_if)::set(null, "uvm_test_top.env", "vif", bus);
run_test("incr_test");
end
endmodule
Prints: check_phase at 110 ns: sent=3 checked=3 PASS: the objection kept the run phase open
Missed Corner
"Zero UVM errors means the test passed."
An empty scoreboard reports no mismatches. The twin's summary shows UVM_ERROR : 0 with nothing sent.
Source Measured: the twin on this question (UVM_ERROR : 0, sent=0), uvm-core 2020.3.1 on Verilator 5.052
Wrong Altitude
"Raise an objection in the driver for every item."
The driver loops forever, so its objection either never drops or toggles on every item. The test or the top sequence knows when the stimulus is finished.
Source Verification Academy, UVM Cookbook, End of Test: who raises objections (PDF p190-191)