Turn a byte and framing options into the half-bit cells a UART transmitter puts on its line.
Hardware context: UART transmitter, receiver and flow-control logic. Recover legal frames and distinguish timing, parity, framing and unread-data loss.
Turn a byte and framing options into the half-bit cells a UART transmitter puts on its line.
Signals in the Timeline
| Signal | Width | Role |
|---|---|---|
case_index | 8 | input of each check |
Full specification
bits is 5..8. Use only the lowest bits of value, least significant first. parity is 0 none, 1 even, 2 odd. Start is two low cells.
Even parity makes the XOR of data and parity zero; odd makes it one. Append stop_half high cells, set length to the number of used cells, and clear unused high cells.
The result packs {length[5:0],cells[23:0]}. This is a digital frame encoder; baud generation and receiver tolerance are separate exercises.
Examples
Example 1
8N1- Input
value=0x55, bits=8, parity=0, stop_half=2
- Output
half_bit_cells = 'b000011001100110011001100, length = 20
Two low start cells precede 16 data cells; 2 high stop cells make 20 cells total.
Example 2
Even Parity- Input
value=0xa5, bits=8, parity=1, stop_half=2
- Output
half_bit_cells = 'b001100110011000011001100, length = 22
Two low start cells precede 16 data cells and two parity cells; 2 high stop cells make 22 cells total.
Example 3
Five Data, 1.5 Stop- Input
value=0x15, bits=5, parity=0, stop_half=3
- Output
half_bit_cells = 'b000000000111110011001100, length = 15
Two low start cells precede 10 data cells; 3 high stop cells make 15 cells total.
Constraints and Contract
- Implement combinational uart_frame. Cell 0 is earliest. Each start, data or parity bit occupies two identical half-bit cells. stop_half selects 2, 3 or 4 high cells.
Hints
Hint 1
Write down which device owns each wire at the observation edge.
Hint 2
Separate framing and data state; decide what a new frame resets.
Hint 3
Check the shortest legal transfer and the boundary where a counter wraps.
What the grader checks: The fixture drives real pins through the shared serial library. Results check the specified digital contract. Electrical rise time, analog noise and hardware CDC signoff are outside this simulation.
7 checks on Icarus Verilog · browser. Run the examples first, then check the full regression. The suite is local and inspectable. A passing result establishes the tested cases, not a proof for all possible inputs.
See all 1 steps and the final capstone