The Frame: Start, Data, Parity, Stop
Draw a UART frame from memory, send it least significant bit first, add even or odd parity, and say what the stop bits are for.
- Lesson
- P6.2
- Time
- 30 min
- Runs on
- Your browser
- Check
- 5 questions
A data logger received 0xAA for every 0x55 and 0x33 for every 0xCC. Its transmitter was a hand-written shift register that sent the most significant bit first, because its author had just finished an SPI block. UART sends the least significant bit first, and every palindromic test byte had passed.
Read phases and sample points (transmitter half bit)
- start: columns 2 through 3.
- data 0: columns 4 through 5.
- data 1: columns 6 through 7.
- data 2: columns 8 through 9.
- data 3: columns 10 through 11.
- data 4: columns 12 through 13.
- data 5: columns 14 through 15.
- data 6: columns 16 through 17.
- data 7: columns 18 through 19.
- stop: columns 20 through 21.
- rx sampled at 4.688, 4.813, 4.938, 6.688, 6.813, 6.938, 8.688, 8.813, 8.938, 10.688, 10.813, 10.938, 12.688, 12.813, 12.938, 14.688, 14.813, 14.938, 16.688, 16.813, 16.938, 18.688, 18.813, 18.938, 20.688, 20.813, 20.938.
- Cycle 0
Idle: the line rests at 1. A receiver can wait here for ever without seeing anything.
- Cycle 2
The start bit is a 0. It is the one edge the receiver can count on, and it must differ from idle to be an edge at all.
- Cycle 4
Data bit 0 first: for 0x55 (0101 0101) that is a 1.
- Cycle 18
Data bit 7 last, a 0. Eight data bits take eight bit-times.
- Cycle 20
The stop bit is a 1, so the next start bit is a falling edge again.
Generated and decoded back. Bands name each bit; the three dots per bit are the receiver’s vote ticks, near the middle (lesson P6.3 shows how it finds them).
The Parts of a Frame
Read the diagram as text
- Idle: line at 1
- Start bit: one 0
- Data bits: 5 to 8, bit 0 first
- Parity bit: optional: even or odd
- Stop time: 1, 1.5 or 2 bits of 1
- Idle or next start: a falling edge again
- Idle → Start bit
- Start bit → Data bits
- Data bits → Parity bit
- Parity bit → Stop time
- Stop time → Idle or next start
Settings such as 8N1, 8E1 and 7E1 name the data bits, the parity (N none, E even, O odd) and the stop time.
Every frame on this site follows that order: idle 1, a start bit of 0, five to eight data bits, an optional parity bit, then a stop time of 1. The bench's transmitter has settings bits, parity and stop_bits, and the receiver has its own copy.
Least Significant Bit First
Put 0xAA beside 0x55 and the two frames are mirror images in time. A transmitter that sends the most significant bit first turns one into the other, and nothing else on the wire looks wrong.
Read phases and sample points (transmitter half bit)
- start: columns 2 through 3.
- data 0: columns 4 through 5.
- data 1: columns 6 through 7.
- data 2: columns 8 through 9.
- data 3: columns 10 through 11.
- data 4: columns 12 through 13.
- data 5: columns 14 through 15.
- data 6: columns 16 through 17.
- data 7: columns 18 through 19.
- stop: columns 20 through 21.
- rx sampled at 4.688, 4.813, 4.938, 6.688, 6.813, 6.938, 8.688, 8.813, 8.938, 10.688, 10.813, 10.938, 12.688, 12.813, 12.938, 14.688, 14.813, 14.938, 16.688, 16.813, 16.938, 18.688, 18.813, 18.938, 20.688, 20.813, 20.938.
Generated and decoded back. Compare with the opening figure: the data bits are reversed, start and stop are the same.
Bench defaults
send_byte(8'h55);
send_byte(8'h33);Measured: UART 55 ok, UART 33 ok.
tx0.lsb_first = 0: most significant bit first
tx0.lsb_first = 0;
send_byte(8'h55);
send_byte(8'h33);Measured: UART aa ok, UART cc ok. No error flag anywhere.
The monitor is right and the transmitter is wrong. Every frame is well formed, so only a byte that is not its own mirror image shows the bug. Here 0x55 and 0x33 do, while 0xA5, 0x3C, 0x00 and 0xFF do not.
Parity: One Bit of Checking
0xA5 has four 1s. Even parity sends 0, so the count of 1s including the parity bit is even. Odd parity sends 1. The receiver counts again and flags PE if its count disagrees.
Read phases and sample points (transmitter half bit)
- start: columns 2 through 3.
- data 0: columns 4 through 5.
- data 1: columns 6 through 7.
- data 2: columns 8 through 9.
- data 3: columns 10 through 11.
- data 4: columns 12 through 13.
- data 5: columns 14 through 15.
- data 6: columns 16 through 17.
- data 7: columns 18 through 19.
- even parity: columns 20 through 21.
- stop: columns 22 through 23.
- rx sampled at 4.688, 4.813, 4.938, 6.688, 6.813, 6.938, 8.688, 8.813, 8.938, 10.688, 10.813, 10.938, 12.688, 12.813, 12.938, 14.688, 14.813, 14.938, 16.688, 16.813, 16.938, 18.688, 18.813, 18.938, 20.688, 20.813, 20.938, 22.688, 22.813, 22.938.
Generated and decoded back. Even parity: the parity bit after data 7 is 0.
Read phases and sample points (transmitter half bit)
- start: columns 2 through 3.
- data 0: columns 4 through 5.
- data 1: columns 6 through 7.
- data 2: columns 8 through 9.
- data 3: columns 10 through 11.
- data 4: columns 12 through 13.
- data 5: columns 14 through 15.
- data 6: columns 16 through 17.
- data 7: columns 18 through 19.
- odd parity: columns 20 through 21.
- stop: columns 22 through 23.
- rx sampled at 4.688, 4.813, 4.938, 6.688, 6.813, 6.938, 8.688, 8.813, 8.938, 10.688, 10.813, 10.938, 12.688, 12.813, 12.938, 14.688, 14.813, 14.938, 16.688, 16.813, 16.938, 18.688, 18.813, 18.938, 20.688, 20.813, 20.938, 22.688, 22.813, 22.938.
Odd parity: the same data, parity bit 1. The frame is one bit longer than 8N1.
| Run | Transmitter | Receiver | Measured |
|---|---|---|---|
| Both even | parity = 1 | parity = 1 | UART a5 ok, RX a5 ok |
| Mismatched settings | parity = 2 (odd) | parity = 1 (even) | UART a5 ok, RX a5 PE |
| One flipped bit | parity_wrong_sense = 1 | parity = 1 | UART a5 PE, RX a5 PE |
| Two flipped bits | 0xA6 sent: 0xA5 with bits 0 and 1 flipped | parity = 1 | UART a6 ok, RX a6 ok |
UART lines are the wire monitor, RX lines the receiver. 0xA6 still has four 1s, so a frame with two bits flipped in transit passes parity.
Parity catches any single flipped bit and misses any even number of them. It is a smoke alarm. A protocol that needs real protection adds a checksum or CRC on top.
Stop Bits and Frame Length
The stop time is idle that the transmitter promises before the next start. It may be 1, 1.5 or 2 bit-times. The bench measured each format as the gap between two back-to-back frames.
| Format | Data bits | Parity | Stop | Ticks per frame | Bit-times |
|---|---|---|---|---|---|
| 8N1 | 8 | none | 1 | 160 | 10 |
| 8E1 | 8 | even | 1 | 176 | 11 |
| 8N2 | 8 | none | 2 | 176 | 11 |
| 7E1 | 7 | even | 1 | 160 | 10 |
| 5N1.5 | 5 | none | 1.5 | 120 | 7.5 |
Measured: one tick is one receiver clock, sixteen to a bit. 8E1 and 8N2 are the same length; 7E1 is as long as 8N1.
The receiver checks only the first stop bit, whatever the setting. A stop cut to a quarter bit (tx0.short_stop = 1) with the next frame right behind it gives UART a5 FE, RX a5 FE: the stop sample lands in the next start bit. The frame after it is read from the wrong edge, UART fe ok, RX fe ok. Why anyone sends two stop bits, lesson P6.4 measures.
Where You Will Meet It
Consoles run 8N1; some industrial links run 8E1 or 7E1. A UART block in a design has the same settings as registers, and a bench must cover all of them: a transmitter bug in one format hides in the others.
Asked in interviews: the frame
Draw an 8N1 frame for 0x41.
Idle 1, start 0, then 1 0 0 0 0 0 1 0 (bit 0 first), stop 1: 10 bit-times.
What does parity catch?
Any odd number of flipped bits. Two flipped bits leave the count of 1s unchanged and pass.
Does the receiver check two stop bits?
A receiver checks the first; the second is idle time the transmitter promises.
Try It
Each byte gives two lines: the wire monitor's UART line and the receiver's RX line. take = 1 reads every byte as soon as it lands, so the receiver's one-byte holding register never fills.
Add tx0.lsb_first = 0; before the first send_byte: 0x55 and 0xAA swap, and 0xA5 is unchanged. Then try tx0.parity = 1; rx0.parity = 1; and tx0.parity = 2; with the receiver still at 1.
UART 55 ok RX 55 ok UART aa ok RX aa ok UART a5 ok RX a5 okRead included file: uart_tx.sv
`timescale 1ns/1ps
module uart_tx(output reg tx=1);
real error=0.0; int bits=8, parity=0; real stop_bits=1.0;
bit lsb_first=1, parity_includes_start=0, parity_includes_stop=0, parity_wrong_sense=0, short_stop=0, no_idle_between=0;
task automatic bit_time(input bit v); tx=v; #(16.0*(1.0+error)); endtask
task automatic send_byte(input byte unsigned value);
bit p; p=(parity==2);
bit_time(0);
for(int b=0;b<bits;b++) begin bit_time(value[lsb_first?b:bits-1-b]); p=p^value[b]; end
if(parity!=0) bit_time(p ^ parity_includes_stop ^ parity_wrong_sense);
tx=1; #(16.0*(1.0+error)*(short_stop?0.25:stop_bits));
// no_idle_between is a legal back-to-back frame control, not a fault.
if(!no_idle_between) #(16.0*(1.0+error));
endtask
task automatic send_break(); tx=0; #(200*16); tx=1; #32; endtask
task automatic set_error(input real e); error=e; endtask
endmodule
Read included file: uart_rx.sv
`timescale 1ns/1ps
module uart_rx(input wire clk, rst_n, rx, take,
output reg [7:0] data=0, output reg valid=0, frame_err=0, parity_err=0, overrun=0, break_seen=0, frame_done=0);
int bits=8, parity=0; real stop_bits=1.0;
bit trace=0;
bit parity_includes_start=0; // XOR of the zero-valued START is an equivalent control.
bit sample_at_edge=0, qualify_1_tick=0, no_vote=0, no_resync=0, rearm_on_low=0, stop_as_data=0, no_overrun_flag=0, parity_includes_stop=0;
int state=0, low_run=0, left_ticks=0, index=0, votes=0, frames=0, ticks=0, next_data_tick=0;
bit armed=1, sampled=0, p=0, pe=0, pending_zero_fe=0; reg [7:0] shift=0;
always @(posedge clk) begin
frame_done=0;
if(!rst_n) begin state=0;low_run=0;left_ticks=0;index=0;votes=0;valid=0;data=0;frame_err=0;parity_err=0;overrun=0;break_seen=0;armed=1;frames=0;ticks=0;next_data_tick=0;pending_zero_fe=0; end
else begin
ticks++;
if(take)valid=0;
low_run=rx?0:low_run+1;
if(rx)break_seen=0;
if(low_run>=176&&!rearm_on_low)begin break_seen=1;state=4;pending_zero_fe=0;end
if(state==4)begin if(rx)begin
if(pending_zero_fe)begin
if(valid&&!no_overrun_flag)overrun=1;
data=0;valid=1;frame_err=1;parity_err=pe;frames++;frame_done=1;pending_zero_fe=0;
end
state=0;armed=1;
end end
else if(state==0)begin
if(rx)begin armed=1;end
else if(armed&&low_run>=(qualify_1_tick?1:8))begin
state=1;left_ticks=sample_at_edge?8:16;index=0;shift=0;p=(parity==2)^parity_includes_stop;votes=0;pe=0;
// Fault: later frames keep the first frame's free-running schedule.
// At nominal back-to-back pacing it can work; a new START must normally
// reset this timing so baud error cannot accumulate across frames.
if(no_resync&&frames>0)begin
while(next_data_tick<=ticks)next_data_tick+=16*(1+bits+(parity!=0))+$rtoi(16*stop_bits);
left_ticks=next_data_tick-ticks;
end else next_data_tick=ticks+left_ticks;
next_data_tick+=16*(1+bits+(parity!=0))+$rtoi(16*stop_bits);
end
end else begin
if(left_ticks<=3)votes=votes+(rx?1:0);
left_ticks=left_ticks-1;
if(left_ticks==0)begin
sampled=no_vote?rx:(votes>=2);votes=0;left_ticks=16;
if(trace)$display("UART SAMPLE t=%0t state=%0d bit=%0d value=%0d",$time,state,index,sampled);
if(state==1)begin shift[index]=sampled;p=p^sampled;index=index+1;if(index==bits)state=parity==0?3:2;end
else if(state==2)begin pe=(sampled!=p);state=3;end
else begin
if(shift==0&&!sampled&&!rearm_on_low)pending_zero_fe=1;
else begin
if(valid&&!no_overrun_flag)overrun=1;
data=stop_as_data?{sampled,shift[7:1]}:shift;
frame_err=!sampled;parity_err=pe;valid=1;frames=frames+1;frame_done=1;
end
state=(sampled||rearm_on_low)?0:4;armed=1;
end
end
end
end
end
endmodule
Read included file: uart_flow.sv
`timescale 1ns/1ps
module uart_flow(input wire clk,rst_n,push,pop,cts_n,input wire [7:0] din,
output wire rts_n,output wire send,output wire [7:0] dout,output reg overrun=0);
reg [7:0] fifo[0:15]; int head=0,count=0,trigger=12;
bit cts_ignored=0,trigger_off_by_one=0;
assign rts_n=count>=(trigger+(trigger_off_by_one?1:0));
assign send=count>0&&(!cts_n||cts_ignored);
assign dout=count>0?fifo[head]:8'h00;
always @(posedge clk)begin
if(!rst_n)begin head=0;count=0;overrun=0;end
else begin
if(pop&&send)begin head=(head+1)%16;count=count-1;end
if(push)begin if(count==16)overrun=1;else begin fifo[(head+count)%16]=din;count=count+1;end end
end
end
endmodule
Read included file: uart_checker.sv
`timescale 1ns/1ps
module uart_checker(input wire clk,rx,valid,frame_err,parity_err,input wire [7:0] data,input wire frame_done);
int broken=0,received=0;
task automatic expect_byte(input byte unsigned wanted,input bit fe=0,pe=0);
if(!valid||data!==wanted||frame_err!==fe||parity_err!==pe)begin broken++;$display("UART CHECK got=%02h valid=%b FE=%b PE=%b expected=%02h FE=%b PE=%b",data,valid,frame_err,parity_err,wanted,fe,pe);end
endtask
always @(negedge clk)if(frame_done)received++;
endmodule
Read included file: uart_mon.sv
`timescale 1ns/1ps
// Independent wire decoder: completion is reported after the stop sample, never at START.
module uart_mon(input wire rx);
int bits=8,parity=0; real bit_period=16.0; int frames=0; bit trace=0;
reg [7:0] value; bit p,pe,fe;realtime began;
initial forever begin
@(negedge rx);began=$realtime; #(bit_period/2); if(rx==0)begin
value=0;p=(parity==2);pe=0;
for(int i=0;i<bits;i++)begin #(bit_period);value[i]=rx;p=p^rx;end
if(parity!=0)begin #(bit_period);pe=(rx!=p);end
#(bit_period);fe=!rx;
if(value==0&&fe)begin
while(rx==0&&$realtime-began<11*bit_period)#(bit_period/16);
if(rx==0)begin wait(rx==1);if(trace)$display("UART -- BREAK");end
else begin frames++;if(trace)$display("UART 00 FE");end
end
else begin frames++;if(trace)$display("UART %02h %s",value,fe?"FE":pe?"PE":"ok");end
end
end
endmodule
Read included file: uart_tasks.svh
task automatic send_byte(input byte unsigned b); tx0.send_byte(b); endtask
task automatic send_break(); tx0.send_break(); endtask
task automatic set_error(input real e); tx0.set_error(e); endtask
task automatic consume(); @(negedge clk);take=1;@(negedge clk);take=0;endtask
Read included file: p6_lab.svh
// p6_lab.svh: lesson helpers. The wire monitor follows the transmitter's format and rate, so its
// UART line shows what was sent; the RX line shows what the receiver under test delivered.
bit rx_log = 1, sample_log = 0;
int ticks = 0, edge_tick = 0, last_left = 0, last_state = 0, last_index = 0;
always @(posedge clk) ticks++;
always @(negedge rx) if (rx0.state == 0) edge_tick = ticks;
always @(tx0.parity) mon.parity = tx0.parity;
always @(tx0.bits) mon.bits = tx0.bits;
always @(tx0.error) mon.bit_period = 16.0 * (1.0 + tx0.error);
always @(negedge clk) begin
if (sample_log && last_left == 1 && rx0.left_ticks == 16) begin
if (last_state == 1) $display("tick %0d: data %0d sample reads %b", ticks - edge_tick, last_index, rx0.sampled);
else if (last_state == 2) $display("tick %0d: parity sample reads %b", ticks - edge_tick, rx0.sampled);
else $display("tick %0d: stop sample reads %b", ticks - edge_tick, rx0.sampled);
end
last_left = rx0.left_ticks; last_state = rx0.state; last_index = rx0.index;
end
// The RX line is printed one bit-time after the receiver's stop sample, after the monitor's line.
always @(rx0.frames) if (rx_log) begin
#16;
if (overrun) $display("RX %02h %s overrun", data, frame_err ? "FE" : parity_err ? "PE" : "ok");
else $display("RX %02h %s", data, frame_err ? "FE" : parity_err ? "PE" : "ok");
end
always @(posedge break_seen) if (rx_log) begin wait (rx == 1); #16 $display("RX break"); end
// A low pulse of the given number of ticks on the idle line.
task automatic glitch(input int width); tx0.tx = 0; #(width); tx0.tx = 1; endtask
// Send a byte and pull the line low for `width` ticks ending at receiver tick `at` after its start edge
// (tick n is the n-th clock edge after the edge), then give the line back its level.
int hit_at = 0, hit_width = 0; reg hit_level = 1; event hit_go;
always @(hit_go) begin
#(hit_at - 0.5 - hit_width + 0.25); hit_level = tx0.tx; tx0.tx = 0; #(hit_width); tx0.tx = hit_level;
end
task automatic send_hit(input byte unsigned b, input int at, input int width);
hit_at = at; hit_width = width; -> hit_go; send_byte(b);
endtask
Check Yourself
Remember
- A frame is idle 1, a start bit of 0, five to eight data bits sent bit 0 first, optional parity, and a stop time of 1.
- A transmitter that sends the most significant bit first mirrors every byte, and palindromic bytes hide it.
- Parity catches one flipped bit and misses two.
- Stop bits are idle time the transmitter promises; the receiver checks the first one.
- 8N1 is ten bit-times on the wire; 8E1 and 8N2 are eleven.
Practice
- Encode a UART Frame Implement · Easy