Implement the sampled condition detector that marks transaction boundaries without mistaking low-clock data changes for START or STOP.
Hardware context: Open-drain I2C controllers and register targets. Preserve ninth-bit ownership, stretching, arbitration, combined reads and bounded recovery.
Implement the sampled condition detector that marks transaction boundaries without mistaking low-clock data changes for START or STOP.
Signals in the Timeline
| Signal | Width | Role |
|---|---|---|
scl | 1 | stimulus, the same for every design |
sda | 1 | stimulus, the same for every design |
Full specification
Pulse start for one system tick when SDA falls while sampled SCL is high. Pulse restart on the same tick if busy was already set. Both ordinary and repeated START set busy.
Pulse stop when SDA rises while SCL is high, then clear busy. SDA edges under low SCL have no framing effect.
Reset clears all outputs and sets the previous SDA sample high. This is a synchronous observation model; a board implementation needs its own input synchronization.
Examples
Example 1
Ordinary Transaction- Input
10 → 00 → 01 → 11
- Output
starts = 1, restarts = 0, busy = yes, stops = 0
A falling SDA under high SCL starts a transaction. The current busy state distinguishes repeated START; only a high-clock rising SDA ends it.
Example 2
Repeated START- Input
10 → 00 → 01 → 11 → 10
- Output
starts = 2, restarts = 1, busy = yes, stops = 0
A falling SDA under high SCL starts a transaction. The current busy state distinguishes repeated START; only a high-clock rising SDA ends it.
Example 3
STOP Releases Busy- Input
10 → 00 → 10 → 11
- Output
starts = 1, restarts = 0, busy = no, stops = 1
A falling SDA under high SCL starts a transaction. The current busy state distinguishes repeated START; only a high-clock rising SDA ends it.
Constraints and Contract
- Inputs scl and sda are synchronized samples. At most one physical transition occurs between samples. Reset establishes an idle-high previous SDA sample.
Hints
Hint 1
Write down which device owns each wire at the observation edge.
Hint 2
Separate framing and data state; decide what a new frame resets.
Hint 3
Check the shortest legal transfer and the boundary where a counter wraps.
What the grader checks: The fixture drives real pins through the shared serial library. Results check the specified digital contract. Electrical rise time, analog noise and hardware CDC signoff are outside this simulation.
The submitted design must synthesize with 0 latches and no combinational loop. Counts come from the pinned open-source synthesis flow. They are proxies for logic size and depth, not physical area or timing.
5 checks on Icarus Verilog + Yosys · server. Run the examples first, then check the full regression. The suite is local and inspectable. A passing result establishes the tested cases, not a proof for all possible inputs.
See all 1 steps and the final capstone