Build the receive-and-ACK slice for an always-ready target. Assemble MSB-first bytes and pull SDA low only for their ninth clocks.
Hardware context: Open-drain I2C controllers and register targets. Preserve ninth-bit ownership, stretching, arbitration, combined reads and bounded recovery.
Build the receive-and-ACK slice for an always-ready target. Assemble MSB-first bytes and pull SDA low only for their ninth clocks.
Signals in the Timeline
| Signal | Width | Role |
|---|---|---|
scl | 1 | stimulus, the same for every design |
sda | 1 | stimulus, the same for every design |
Full specification
A high-SCL falling SDA starts or restarts reception and resets the partial bit counter. A high-SCL rising SDA ends reception.
Sample eight data bits on rising SCL, then publish value and increment bytes. Drive pull_low on the following falling SCL, hold through the ninth rising edge, and release on its falling edge.
The immutable controller releases SDA on ACK. The grader checks byte values, ACK responses and release after the ninth clock. Analog filtering and register decoding are outside this slice.
Examples
Example 1
Receive a0 Then 96- Input
Two bytes followed by STOP
- Output
data = 0xa0, second_byte = 0x96, acks = 3, released = yes, byte_count = 2
Both complete bytes are acknowledged. The target releases SDA after each ninth clock and reports exactly two received bytes.
Example 2
Receive 0 Then Ff- Input
Two bytes followed by STOP
- Output
data = 0x0, second_byte = 0xff, acks = 3, released = yes, byte_count = 2
Both complete bytes are acknowledged. The target releases SDA after each ninth clock and reports exactly two received bytes.
Example 3
Receive Ff Then 0- Input
Two bytes followed by STOP
- Output
data = 0xff, second_byte = 0x0, acks = 3, released = yes, byte_count = 2
Both complete bytes are acknowledged. The target releases SDA after each ninth clock and reports exactly two received bytes.
Constraints and Contract
- Implement event-driven i2c_byte_rx for the teaching bench. Every complete byte is accepted, including the first byte after START; address selection belongs to the next exercise.
Hints
Hint 1
Write down which device owns each wire at the observation edge.
Hint 2
Separate framing and data state; decide what a new frame resets.
Hint 3
Check the shortest legal transfer and the boundary where a counter wraps.
What the grader checks: The fixture drives real pins through the shared serial library. Results check the specified digital contract. Electrical rise time, analog noise and hardware CDC signoff are outside this simulation.
4 checks on Icarus Verilog · browser. Run the examples first, then check the full regression. The suite is local and inspectable. A passing result establishes the tested cases, not a proof for all possible inputs.
See all 2 steps and the final capstone