Interview Question · Code Reading

Reading a Signed Field in C

L1 JuniorL2 Mid-Leveldpidata types

The interviewer asks

What does this print? The SystemVerilog value is -5.

systemverilog

// SystemVerilog
import "DPI-C" function int c_offset(input bit signed [11:0] v);
bit signed [11:0] trim = -5;
initial $display("C value=%0d", c_offset(trim));

// C
extern "C" int c_offset(const svBitVecVal* v) { return (int)v[0]; }

Reveal the Model Answer

It prints 4091, not -5. A packed vector such as bit signed [11:0] crosses as an array of 32-bit svBitVecVal words. The 12 bits sit at the bottom of word 0, and nothing copies the sign bit upward. So C reads 0xFFB as a positive number. Sign-extend from bit 11 in C, or use shortint or int, which cross as C short and int with their sign.

SystemVerilog formal	C type in the generated header
`bit` / `logic`	`svBit` / `svLogic` (one byte)
`byte` / `byte unsigned`	`char` / `unsigned char`
`shortint` / `int` / `int unsigned`	`short` / `int` / `unsigned int`
`longint`	`long long`
`real`	`double`
`chandle` / `string`	`void` / `const char`
input `bit [N:0]`	`const svBitVecVal*` (32-bit words)
input `logic [N:0]`	`const svLogicVecVal*` (aval, bval pairs)
`output int`	`int*`
open array `byte unsigned d[]`	`const svOpenArrayHandle`

Read from the header Verilator 5.052 generated. The header, not memory, is the authority for a given build.

Self-Check

Tick each key point you covered in your answer.

Key point 1 It prints 4091, not -5. Key point 2 A packed vector such as bit signed [11:0] crosses as an array of 32-bit svBitVecVal words. Key point 3 The 12 bits sit at the bottom of word 0, and nothing copies the sign bit upward. Key point 4 So C reads 0xFFB as a positive number. Key point 5 Sign-extend from bit 11 in C, or use shortint or int, which cross as C short and int with their sign.

What Interviewers Listen For (Junior)

Predicts a large positive number and explains that the vector arrives as words, not as a C int.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfCompareScale It

Reading a Signed Field in C
WhyWhy Vectors Arrive as PointersL2 Mid-Level
Why does an input bit [7:0] arrive as const svBitVecVal*, while byte unsigned arrives as a plain unsigned char?

Reveal the Model Answer

A packed vector can have any width. So the standard gives every vector one form: an array of 32-bit words, passed by reference. byte, int and longint have a fixed size, so each has its own C type and travels by value. The generated header shows which form each argument got.

Self-Check
Tick each key point you covered in your answer.
Key point 1 A packed vector can have any width. Key point 2 So the standard gives every vector one form: an array of 32-bit words, passed by reference. Key point 3 byte, int and longint have a fixed size, so each has its own C type and travels by value. Key point 4 The generated header shows which form each argument got.

Misconception

"A bit [7:0] and a byte unsigned are the same thing to C."

They hold the same 8 bits in SystemVerilog, but they cross differently. A C body written for one does not match the prototype of the other.

Source ASIC Point engine notes (prototypes in the Vtb__Dpi.h that Verilator 5.052 generated, 2026-11-08)
- Lesson D1.3Packed Vectors and Four-State Bits
What IfFour-State Bits in CL2 Mid-Level
Asked if the bus can carry x or z

What if the bus may carry x or z? How does C see them?

Reveal the Model Answer

Each 32 bits of a logic vector cross as one svLogicVecVal with two words. A bval bit of 0 means the bit is known, and aval holds its value. A bval bit of 1 means unknown: aval 1 is x and aval 0 is z. A checker that rejects unknowns must test bval, not aval.

bval aval Bit value

0 0 0
0 1 1
1 0 z
1 1 x

The encoding of one bit in svLogicVecVal.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Each 32 bits of a logic vector cross as one svLogicVecVal with two words. Key point 2 A bval bit of 0 means the bit is known, and aval holds its value. Key point 3 A bval bit of 1 means unknown: aval 1 is x and aval 0 is z. Key point 4 A checker that rejects unknowns must test bval, not aval.
Tool as Truth

"C saw no bval bits on Verilator, so the bus never carries x."

Verilator is a two-state simulator. It turns x into 0 before the call, so C cannot see it there. The twin drives four x bits and C counts none.

Run It

A bus with an undriven upper nibble, passed as logic [7:0].

RUNVerilator + C/C++ over DPI · simulator service

Edit the code, then run it

Expected: aval=05 bval=00 unknown bits seen by C=0 FAIL: the x never reached C; this two-state engine turned it into 0 before the call
- Lesson D1.3Packed Vectors and Four-State Bits
Scale ItTesting the X Path on a Two-State SimulatorL3 Senior
Your main simulator is two-state, but the C checker must reject x. How do you verify that path?

Reveal the Model Answer

Test the C function on its own, with a small C test that builds svLogicVecVal values with bval bits set. Run the DPI x tests on a four-state simulator, if the project has one. Where unknowns matter in the design, also carry an explicit valid mask, which works on both kinds of simulator.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Test the C function on its own, with a small C test that builds svLogicVecVal values with bval bits set. Key point 2 Run the DPI x tests on a four-state simulator, if the project has one. Key point 3 Where unknowns matter in the design, also carry an explicit valid mask, which works on both kinds of simulator.

What Interviewers Listen For (Senior)
Splits the problem into a C unit test and a four-state run. Does not count a two-state pass as x coverage.

Missed Corner

"The two-state run passed, so the x check is covered."

No x ever reached the checker in that run. A passing check that never saw its input proves nothing about it.

Source Lesson D1.3 review claims (known_low returns 1 for 32'hx on Verilator 5.052)
- Lesson D1.3Packed Vectors and Four-State Bits
CompareA Longint Compared with a 64-Bit VectorL1 JuniorL2 Mid-Level
Compare passing a 64-bit value as longint with passing it as bit [63:0].

Reveal the Model Answer

A longint crosses by value as a C long long, ready to use. A bit [63:0] crosses as two svBitVecVal words. Word 0 holds bits 31:0 and word 1 holds bits 63:32, so C must join them with a shift. Prefer longint for numbers, and vectors for fields wider than 64 bits.

Self-Check
Tick each key point you covered in your answer.
Key point 1 A longint crosses by value as a C long long, ready to use. Key point 2 A bit [63:0] crosses as two svBitVecVal words. Key point 3 Word 0 holds bits 31:0 and word 1 holds bits 63:32, so C must join them with a shift. Key point 4 Prefer longint for numbers, and vectors for fields wider than 64 bits.

Misconception

"Word 0 is the top half, like the left side of the declaration."

Word order follows significance: word 0 is the least significant 32 bits. Reading it as the top half swaps the halves.

Source Lesson D1.3 review claims (word_of returns 55667788 for word 0 of 64'h01020304_55667788)
- Lesson D1.2Types, Outputs and a Status Code
- Lesson D1.3Packed Vectors and Four-State Bits

bval	aval	Bit value
0	0	0
0	1	1
1	0	z
1	1	x

What People Get Wrong

Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.

Misconception

"C gets -5, because the field is declared signed."

Signedness does not travel with a packed vector. C receives raw words, and the bits above bit 11 are not a copy of the sign.

Run It

A 12-bit signed trim value of -5 passed to C, which reads word 0.

RUNVerilator + C/C++ over DPI · simulator service

Edit the code, then run it

Expected: SystemVerilog value=-5, C value=4091 FAIL: C read the 12 bits as an unsigned word; nothing copied the sign bit upward

module tb;
  import "DPI-C" function int c_offset(input bit signed [11:0] v);
  bit signed [11:0] trim = -5;
  int got;
  initial begin
    got = c_offset(trim);
    $display("SystemVerilog value=%0d, C value=%0d", trim, got);
    if (got != -5) $display("FAIL: C read the 12 bits as an unsigned word; nothing copied the sign bit upward");
    else $display("PASS: C sign-extended from bit 11 and got -5");
    $finish;
  end
endmodule

See the Fix

module tb;
  import "DPI-C" function int c_offset(input bit signed [11:0] v);
  bit signed [11:0] trim = -5;
  int got;
  initial begin
    got = c_offset(trim);
    $display("SystemVerilog value=%0d, C value=%0d", trim, got);
    if (got != -5) $display("FAIL: C read the 12 bits as an unsigned word; nothing copied the sign bit upward");
    else $display("PASS: C sign-extended from bit 11 and got -5");
    $finish;
  end
endmodule

Prints: SystemVerilog value=-5, C value=-5 PASS: C sign-extended from bit 11 and got -5

Misconception

"logic [7:0] reaches C as one byte."

A four-state vector crosses as pairs of words, aval and bval. C must read both to tell 0 and 1 from x and z.

Source IEEE 1800-2017 Annex H (canonical representation of packed arrays: svBitVecVal, svLogicVecVal)

Half-Truth

"int unsigned and int are the same in C, so signedness does not matter."

They map to unsigned int and int. A comparison such as x > 0 gives different answers for the same bits.

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