One Property, Two Clocks

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfCompareScale It

1. One Property, Two Clocks
2. WhyWhy the Next Edge of the New ClockL3 Senior

   Why does the language define the crossing as "the next edge of the new clock" instead of a fixed number of cycles?

   Reveal the Model Answer

   The two clocks have no fixed relation, so "two cycles" has no single meaning across them. The next edge of the destination clock is the earliest moment that domain can observe anything. Every longer wait can then be written inside the destination clock's own subsequence.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The two clocks have no fixed relation, so "two cycles" has no single meaning across them. Key point 2 The next edge of the destination clock is the earliest moment that domain can observe anything. Key point 3 Every longer wait can then be written inside the destination clock's own subsequence.

   Misconception

   "It is defined in terms of the faster clock."

   It always uses the clock of the subsequence that comes next, whichever is faster.

   Source IEEE 1800-2017 §16.13.1

   • Lesson A1.2Clocks and Sampling
3. What IfWhen Both Clocks Are the SameL2 Mid-LevelL3 Senior

   What if clk_a and clk_b are actually the same clock, in phase?

   Reveal the Model Answer

   Then the next strictly later clk_b edge is simply the next clock edge. So @(posedge clk_a) req ##1 @(posedge clk_b) ack behaves like @(posedge clk_a) req ##1 ack. The multiclock form costs nothing when the clocks match, and stays correct if they later split.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Then the next strictly later clk_b edge is simply the next clock edge. Key point 2 So @(posedge clk_a) req ##1 @(posedge clk_b) ack behaves like @(posedge clk_a) req ##1 ack. Key point 3 The multiclock form costs nothing when the clocks match, and stays correct if they later split.

   Misconception

   "With identical clocks, the crossing adds an extra cycle."

   The rule picks the nearest strictly later edge, which is exactly one cycle when the clocks match.

   Source Mehta, SystemVerilog Assertions and Functional Coverage (3rd ed.), §10.2

   • Lesson A1.2Clocks and Sampling
4. CompareA Multiclock Property vs Checking a Synchronised CopyL3 Senior

   Compare writing one multiclock property with first synchronising req into the clk_b domain and writing a single-clock property there.

   Reveal the Model Answer

   The multiclock property states the rule exactly as the spec says, across both domains. The synchronised copy is easier to read and runs on more tools. But it checks the copy, which arrives two or three cycles late. Then the property must allow for that delay. Many teams use the single-clock form for tool support, and keep multiclock properties for formal runs.

   	Multiclock property	Single-clock property on a synchronised copy
   States the rule	Exactly as the spec does	Shifted by the synchronizer delay
   Checks	The real signal	A copy that arrives 2 or 3 cycles late
   Tool support	Narrower	Every tool

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The multiclock property states the rule exactly as the spec says, across both domains. Key point 2 The synchronised copy is easier to read and runs on more tools. Key point 3 But it checks the copy, which arrives two or three cycles late. Key point 4 Then the property must allow for that delay. Key point 5 Many teams use the single-clock form for tool support, and keep multiclock properties for formal runs.

   What Interviewers Listen For (Senior)

   A good senior answer says what the delayed copy hides. It picks the form that the team's actual tools support.

   Missed Corner

   "The synchronised copy changes nothing; it is the same signal."

   It arrives one or more destination cycles later. A tight timing rule written on it can pass when the real rule fails.

   Source Lesson R6.2 (two-flop synchronizer latency)

   • Lesson R6.2The Two-Flop Synchronizer and What It Cannot Carry
5. Scale ItCDC Sign-Off on a Many-Clock SoCL3 SeniorL4 Staff

   How do you sign off clock domain crossings on an SoC with dozens of clocks?

   Reveal the Model Answer

   Start with structural analysis: define the clocks and their relationships. Then let the tool find every crossing and check that each has the right synchronizer for its type. Next comes protocol checking: each scheme's rules, such as hold times and Gray steps, become assertions in formal and simulation. Add reconvergence checks and reviewed waivers. Use metastability injection in simulation to expose designs that assume exact timing.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Start with structural analysis: define the clocks and their relationships. Key point 2 Then let the tool find every crossing and check that each has the right synchronizer for its type. Key point 3 Next comes protocol checking: each scheme's rules, such as hold times and Gray steps, become assertions in formal and simulation. Key point 4 Add reconvergence checks and reviewed waivers. Key point 5 Use metastability injection in simulation to expose designs that assume exact timing.

   Tool as Truth

   "Our regressions pass with all clocks running, so CDC is covered."

   RTL simulation never goes metastable and rarely hits the bad clock phase. CDC needs structural and protocol checks, not only passing tests.

   Source Mehta, ASIC/SoC Functional Design Verification ch. 8.5 (PDF p186-188); Sutherland, RTL Modeling with SystemVerilog ch. 8.1.6

   Wrong Altitude

   A staff-level answer that stops at "run the CDC tool".

   The interviewer wants the flow: constraints, structure, protocol, reconvergence, waiver review and who owns each step.

   • Lesson F5.6CDC and RDC with Formal
   • Lesson R6.2The Two-Flop Synchronizer and What It Cannot Carry