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Designing the Bench for a DMA Engine

L3 SeniorL4 Staffuvmarchitecturetestbench design

The interviewer asks

Design the testbench for a DMA engine. It has an APB register port, an AXI master port to memory, and an interrupt line. What goes where?

Reveal the Model Answer

An APB agent with a register model and explicit prediction programs the DMA. A reactive AXI slave agent answers reads from a memory model and records writes. A predictor reads each programmed transfer from the register model and computes the expected memory writes. A scoreboard compares those with the writes the AXI monitor saw. An interrupt monitor checks when the interrupt rises and clears, and a virtual sequence ties the steps together.

A Testbench for a DMA EngineArrows show transactions and data. The virtual sequence programs the DMA through the APB agent. The predictor works from the register model, and the scoreboard compares its expected writes with the writes the AXI monitor saw.
A testbench for a DMA engineArrows show transactions and data. The virtual sequence programs the DMA through the APB agent. The predictor works from the register model, and the scoreboard compares its expected writes with the writes the AXI monitor saw. sequence Virtual sequence Programs a transfer,then waits for theinterrupt agent APB agent Writes DMAregisters; its monitorfeeds a registerpredictor design DMA engine The design under test agent AXI slave agent Reactive: answersreads from a memorymodel, records writes model Register model Mirror of theprogrammed transfer(explicit prediction) model Predictor Computes the memorywrites the transfermust make checker Scoreboard Expected writes vsobserved writes monitor Interrupt monitor Checks when theinterrupt rises andclears register writesAPB transfersAXI reads, writesobserved writesprogrammed transferexpected writesobserved writesirq line
Read the diagram as text
  • Virtual sequence: Programs a transfer, then waits for the interrupt
  • APB agent: Writes DMA registers; its monitor feeds a register predictor
  • DMA engine: The design under test
  • AXI slave agent: Reactive: answers reads from a memory model, records writes
  • Register model: Mirror of the programmed transfer (explicit prediction)
  • Predictor: Computes the memory writes the transfer must make
  • Scoreboard: Expected writes vs observed writes
  • Interrupt monitor: Checks when the interrupt rises and clears
  • Virtual sequence → APB agent: register writes
  • APB agent → DMA engine: APB transfers
  • DMA engine → AXI slave agent: AXI reads, writes
  • APB agent → Register model: observed writes
  • Register model → Predictor: programmed transfer
  • Predictor → Scoreboard: expected writes
  • AXI slave agent → Scoreboard: observed writes
  • DMA engine → Interrupt monitor: irq line

Each part has one job: stimulus, a reply, a prediction or a check. That split is what lets most of the bench survive at SoC level.

ComponentJobWhy it is separate
APB agent + register modelProgram and read back the DMAReused passive at SoC level, behind a CPU
AXI slave agent (reactive)Answer reads, accept writes, add delays and errorsMemory behaviour is stimulus, not checking
Memory modelHold source data and descriptorsShared by the slave and the predictor
PredictorTurn programmed transfers into expected writesWritten from the spec, not from the RTL
ScoreboardCompare expected and observed writesGives the exact failing transfer
Virtual sequenceProgram, start, wait for the interrupt, checkCoordinates two agents

Each component exists because of one check or one stimulus need.

Self-Check

Tick each key point you covered in your answer.

What Interviewers Listen For (Senior)

A good senior answer draws the agents, the predictor, the scoreboard and the virtual sequence. It justifies each part by what it checks.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfBreak ItCompareScale It

  1. Designing the Bench for a DMA Engine
  2. WhyWhy Memory Is a Reactive AgentL3 Senior

    Why model the memory with a reactive slave agent, rather than a plain SystemVerilog memory module?

    Reveal the Model Answer

    A plain memory module answers the same way every time. A reactive agent takes its responses from sequences, so a test can add wait states, back-pressure and error responses on chosen beats. Its monitor also publishes every transfer for the scoreboard and coverage. The memory storage itself can stay a simple model that both the agent and the predictor read.

    The Design Starts the Conversation; the Sequence AnswersA reactive slave agent answering a bus master. Arrows are item handoffs and pin activity for one request.
    The design starts the conversation; the sequence answersA reactive slave agent answering a bus master. Arrows are item handoffs and pin activity for one request. dut Bus master (DUT) Plain module with afixed script driver Slave driver Moves fields betweenpins and items sequencer Slave sequencer One responder persequencer sequence Respondersequence forever loop, decidesevery reply state Memory model Associative arrayinside the sequence 1. empty request item1.get_next_item(request)2. req, we, addr,wdata2. item_done:finish_item returnsthe filled request3. store or look up3. reply item: rdata,err, wait_cycles4. ack, rdata, err
    1. Tell me what to do (0 ns)

      The responder sends an empty request item with start_item and finish_item. The driver takes it with get_next_item and waits for req.

      Follow the calls, values and waits
      1. call get_next_item: Slave driver → Slave sequencer
      2. data request item: Responder sequence → Slave sequencer
      3. data request item: Slave sequencer → Slave driver
      4. Waiting: Responder sequence — in finish_item(request)
      5. Waiting: Slave driver — waiting for req
    2. This is what the master asked (35 ns)

      Master 0 raised req for its write to 0x10. The driver copies we, addr and wdata into the same object and calls item_done; the responder's finish_item returns.

      Follow the calls, values and waits
      1. data write 0x10 <= 0x5a: Bus master (DUT) → Slave driver
      2. call item_done: Slave driver → Slave sequencer
      3. data request item: Slave sequencer → Responder sequence
      4. Released: Responder sequence
      5. Released: Slave driver
    3. Here is the reply (35 ns)

      The responder stores 0x5a, randomizes a reply item under its constraints and sends it. No simulation time passes.

      Follow the calls, values and waits
      1. data mem[0x10] = 0x5a: Responder sequence → Memory model
      2. data reply item: Responder sequence → Slave driver
      3. Waiting: Responder sequence — in finish_item(reply)
    4. Done (45 ns)

      The driver drives ack, rdata and err for one clock and calls item_done. The master samples ack at 45 ns.

      Follow the calls, values and waits
      1. data ack, err=0: Slave driver → Bus master (DUT)
      2. Released: Bus master (DUT)
      3. Released: Responder sequence
    Read the diagram as text
    • Bus master (DUT): Plain module with a fixed script
    • Slave driver: Moves fields between pins and items
    • Slave sequencer: One responder per sequencer
    • Responder sequence: forever loop, decides every reply
    • Memory model: Associative array inside the sequence
    • Responder sequence → Slave sequencer: 1. empty request item
    • Slave driver → Slave sequencer: 1. get_next_item(request)
    • Bus master (DUT) → Slave driver: 2. req, we, addr, wdata
    • Slave sequencer → Responder sequence: 2. item_done: finish_item returns the filled request
    • Responder sequence → Memory model: 3. store or look up
    • Responder sequence → Slave driver: 3. reply item: rdata, err, wait_cycles
    • Slave driver → Bus master (DUT): 4. ack, rdata, err

    Swap the responder box and only the reply rule changes; the driver and item stay.

    Self-Check

    Tick each key point you covered in your answer.

    Half-Truth

    "A memory module is enough; the DMA only needs data back."

    Then no test can make memory slow or return an error. The DMA's stall and error paths stay untested.

  3. What IfAn Error Response on One Chosen BeatL3 Senior

    What if a test needs the memory to return an error on one beat of one transfer? How does it do that?

    Reveal the Model Answer

    The test starts a different responder sequence on the slave agent. That sequence answers normally until the chosen address and beat, then returns an error response. The driver is unchanged, because the sequence picks the reply. The scoreboard is told the same plan, so it expects the DMA to stop or report.

    Self-Check

    Tick each key point you covered in your answer.

    Wrong Altitude

    "Force the memory output to an error value."

    A force bypasses the protocol and cannot target one beat cleanly. The monitor and coverage never see a legal error response.

  4. CompareEnd-State Check vs Stream CheckL3 Senior

    Compare checking memory contents at the end with checking each write as it happens.

    Reveal the Model Answer

    An end-state check is simple and catches wrong final data. It misses writes outside the buffer that were later overwritten, repeated writes and wrong order. A stream check compares each write as it arrives, so it points at the exact transfer. Many benches do both: stream checks for debug, and an end check as a safety net.

    Self-Check

    Tick each key point you covered in your answer.

  5. What IfA DMA That Follows Descriptors in MemoryL3 Senior

    What if the DMA follows a chain of descriptors that it reads from memory?

    Reveal the Model Answer

    Then the descriptors live in the memory model, and the predictor must read the same memory, not the register model. Build the chain in the test, write it into memory by backdoor, and point the DMA at its head. Check the descriptor reads too, not only the data writes.

    Self-Check

    Tick each key point you covered in your answer.

  6. Break ItThe Bug This Bench Would MissL3 SeniorL4 Staff

    What kind of bug would this bench miss?

    Reveal the Model Answer

    One that the predictor shares with the RTL, such as the same misreading of the descriptor format. Both agree, so every check passes. An independent model author, spec reviews, and a few directed tests with results worked out by hand protect against this.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Staff)

    A good staff answer names a shared misreading of the spec as the main risk of any model-based bench. It plans for an independent model author and spec reviews.

  7. Scale ItWhat of the DMA Bench Survives at SoC LevelL4 Staff

    Scale it: at SoC level, what of this bench survives?

    Reveal the Model Answer

    The APB agent turns passive behind the CPU, and real memory replaces the slave model. The predictor and scoreboard survive if they listen only to monitors. The predictor must read memory through an interface that either the model or a backdoor to real memory can serve. Software or a CPU model replaces the virtual sequence.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Staff)

    A good staff answer designs the predictor's memory access as a swappable interface at block level. Then reuse at SoC level costs only wiring.

What People Get Wrong

Common wrong answers and why they fail.

Wrong Altitude

Lists UVM classes without saying what each one checks.

A class list is not a design. Each component should exist because of a check or a stimulus need.

Half-Truth

"A memory slave that answers every access at once and OK is enough."

A DMA must survive slow memory and error responses. A slave that never stalls and never returns SLVERR never exercises those paths.

Buzzword Without Mechanism

"I would use the standard UVM architecture."

That says nothing about this DMA. Name the agents, the model, what is compared, and when.

Learn It, Then Prove It