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Interview Question · Code Reading
Desired and Mirrored Register Values
The Question
The interviewer asks
The DUT holds CTRL at 0x01 after reset, and auto-prediction is on. What are the desired and mirrored values after each line?
task run_phase(uvm_phase phase);
uvm_status_e status;
regs.reset(); // the DUT also holds CTRL = 01
regs.ctrl.set('h5a);
regs.ctrl.update(status);
regs.ctrl.write(status, 'h33);
void'(regs.ctrl.predict('h77));
regs.ctrl.mirror(status, UVM_CHECK);
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Reveal the Model Answer
set(5a) changes only the desired value; the mirror stays 1, so an update is needed. update() writes 5a on the bus, and the mirror follows. write(33) sets both to 33. predict(77) sets both to 77 in the model only, while the DUT still holds 33. mirror(UVM_CHECK) reads 33, reports a mismatch against 77, and sets both values to 33.
Only update(), write() and mirror() use the bus. set() and predict() change the model alone.
The interview code on the APB bench, printing both values after each step.
0 ns reset() desired=1 mirrored=1 needs_update=0 0 ns set(5a) desired=5a mirrored=1 needs_update=1 25 ns APB write addr=0 data=5a 30 ns update() desired=5a mirrored=5a needs_update=0 55 ns APB write addr=0 data=33 60 ns write(33) desired=33 mirrored=33 needs_update=0 60 ns predict(77) desired=77 mirrored=77 needs_update=0 85 ns APB read addr=0 data=33 90 ns mirror(CHECK) desired=33 mirrored=33 needs_update=0 UVM_ERROR : 1Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer keeps two columns, desired and mirrored. It updates both line by line without mixing them up.
What Interviewers Listen For (Mid-Level)
A good mid-level answer points out that predict() moved no signals on the bus. It then explains why mirror(UVM_CHECK) reports an error.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItBreak ItCompare
- Desired and Mirrored Register Values
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WhyWhy the Register Model Keeps a MirrorL1 Junior
Why keep a mirror at all, when the bench could simply read the register?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Reads cost bus cycles and can have side effects, such as clear-on-read. The mirror tells the bench the expected value at any time, with no extra bus traffic. It also lets
mirror(UVM_CHECK)compare a real read with what the bench believes. That comparison is how the register layer finds register bugs.Which Value Each Bookkeeping Call ChangesArrows show which of a field's two model values each call changes. None of these calls reaches the design; only a bus access does. Illustrative sequenceCallValueReturnWaiting- reset()
Both values become 01, the configured reset value.
Follow the calls, values and waits
- data reset value 01: reset() → Desired value
- data reset value 01: reset() → Mirrored value
- set(5a)
Desired becomes 5a, mirror stays 01, so
needs_update()returns 1.Follow the calls, values and waits
- data v = 5a: set(v) → Desired value
- Waiting: Desired value — 5a requested, mirror 01: needs_update() = 1
- predict(5a)
Both become 5a; the values agree again and
needs_update()returns 0.Follow the calls, values and waits
- data v = 5a: predict(v) → Desired value
- data v = 5a: predict(v) → Mirrored value
- Released: Desired value
- set(22)
A new request: desired becomes 22 while the mirror stays 5a.
Follow the calls, values and waits
- data v = 22: set(v) → Desired value
- Waiting: Desired value — 22 requested, not yet sent
- predict(44)
predict overwrites the pending 22 in the desired value: the lost request.
Follow the calls, values and waits
- data v = 44: predict(v) → Desired value
- data v = 44: predict(v) → Mirrored value
- Released: Desired value
- The design
Nothing above touched it. Changing it needs a bus access; in the state just shown, desired and mirror are both 44, so
update()would send nothing.
Read the diagram as text
- set(v): A request: what the test wants next
- predict(v): A record: what the design is believed to hold
- reset(): The model's side of a design reset
- Desired value: Read with get()
- Mirrored value: Read with get_mirrored_value()
- incr_csr.ctrl: Unchanged by every call on the left
- set(v) → Desired value: desired = v
- predict(v) → Desired value: desired = v
- predict(v) → Mirrored value: mirror = v
- reset() → Desired value: reset value
- reset() → Mirrored value: reset value
- Desired value → incr_csr.ctrl: update(), only if values differ
The register ledger without a bus: two model values per field, and a design that only bus accesses change.
Self-Check
Tick each key point you covered in your answer.
- reset()
-
Break ItA DUT Reset the Model Did Not SeeL2 Mid-Level
How does a DUT reset in the middle of the test break the mirror?
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Reveal the Model Answer
The DUT goes back to its reset values, but the model keeps the old mirror. Every later check then fails. Call
regs.reset()when the bench sees the DUT reset, so the model returns to the same reset values.Self-Check
Tick each key point you covered in your answer.
Misconception
"The register model notices the reset by itself."
The model has no connection to the reset pin. Something in the bench must watch reset and call
reset()on the block.Source uvm-core 2020.3.1 (IEEE 1800.2 library) source, reg/uvm_reg_block.svh (reset() sets each register to its reset value)
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What IfChecking a Register the Hardware ChangesL2 Mid-Level
What if the field is a status counter that the hardware changes by itself?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Its mirror can never be exact, so a check against it fails at random. Configure the field as volatile. In uvm-core that also sets its compare mode to
UVM_NO_CHECK, somirror(UVM_CHECK)skips it. Check the counter some other way, such as a scoreboard that predicts its value from observed events.Self-Check
Tick each key point you covered in your answer.
Half-Truth
"Turn off the check for the whole register."
Other fields in the same register may be plain read-write. Turning off the field, not the register, keeps them checked.
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Comparewrite() vs set() and update()L1 JuniorL2 Mid-Level
Compare
write(v)withset(v)followed byupdate().2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
write(v)always performs a bus write and updates both values.set()plusupdate()lets you change several fields first and then write only the registers that changed. That suits configuring a block from randomized register values. It also avoids writing registers that already hold the right value.Self-Check
Tick each key point you covered in your answer.
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Prove ItSolve U13.2.1: Registers That All Read ZeroSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail.
Misconception
"set() writes the register."
It changes only the desired value inside the model. Nothing moves on the bus until update() or write(). The run shows no APB transfer after set(5a).
Source Measured: the run on this question, uvm-core 2020.3.1 on Verilator 5.052
Misconception
"The mirror is what the DUT holds."
The mirror is the model's best guess of the DUT value. predict(77) made it 77 while the DUT kept 33. Only a read, or a predictor watching the bus, brings it back.
Source uvm-core 2020.3.1 (IEEE 1800.2 library) source, reg/uvm_reg.svh (predict updates the mirror without a bus access)
Half-Truth
"update() always writes the register."
It writes only when the desired value differs from the mirror. A second update() with nothing changed sends no transfer at all.
Source uvm-core 2020.3.1 (IEEE 1800.2 library) source, reg/uvm_reg.svh (update returns early unless needs_update())