Interview Question · Design

Auto vs Explicit Register Prediction

L2 Mid-LevelL3 Senioruvmralprediction

The interviewer asks

Your register model uses auto-prediction. A boot sequence also writes registers directly on the bus. What goes wrong, and how do you set up prediction instead?

Reveal the Model Answer

Auto-prediction updates the mirror only for accesses made through the register model. The boot write is invisible to it, so the mirror stays at the reset value and the next mirror(UVM_CHECK) fails. Use explicit prediction instead: connect a uvm_reg_predictor to the bus monitor. The predictor converts every observed transfer with the adapter and updates the right register. Turn auto-prediction off, so each access is predicted once.

The Boot Write Reaches the Mirror Through the MonitorArrows are items and calls for a boot write that the register model never made. The model learns about it from the pins, through the monitor and the predictor.

Start a raw item
The boot sequence sends a raw item to the sequencer. The map took no part.
Follow the calls, values and waits
1. data boot apb_item: write 0 <- a5: boot_write sequence → APB sequencer + driver
2. Waiting: boot_write sequence — in finish_item until item_done
On the bus25 ns (illustrative)
The design takes a5 at the 25 ns edge.
Follow the calls, values and waits
1. data pwdata = a5 at address 0: APB sequencer + driver → incr_csr.ctrl
Observed25 ns (illustrative)
The monitor sees psel, penable and pready at the 25 ns edge and writes the transfer to its analysis port.
Follow the calls, values and waits
1. data pwdata = a5 at address 0: incr_csr.ctrl → apb_monitor
2. data monitor item t: write 0, a5: apb_monitor → uvm_reg_predictor
Predicted25 ns (illustrative)
The predictor converts the item with the adapter, asks the map which register sits at address 0 and predicts it with the field's write policy. The mirror is a5, and the prediction count is 1.
Follow the calls, values and waits
1. data predict a5: uvm_reg_predictor → regs.ctrl
The boot write returns30 ns (illustrative)
The driver calls item_done and the boot sequence's finish_item returns. The mirror already holds a5.
Follow the calls, values and waits
1. return item_done: APB sequencer + driver → boot_write sequence
2. Released: boot_write sequence

Read the diagram as text

boot_write sequence: Raw apb_item, no register call
APB sequencer + driver: Write of a5 completes at 25 ns
incr_csr.ctrl: a5 after the 25 ns edge
apb_monitor: Samples the completed transfer at 25 ns
uvm_reg_predictor: bus2reg, then the map finds CTRL at address 0
regs.ctrl: Mirror and desired become a5

boot_write sequence → APB sequencer + driver: apb_item
APB sequencer + driver → incr_csr.ctrl: APB write
incr_csr.ctrl → apb_monitor: pins sampled
apb_monitor → uvm_reg_predictor: ap.write(t)
uvm_reg_predictor → regs.ctrl: predict a5 (write policy)

With explicit prediction, every successful access the monitor sees to a mapped register reaches the mirror. Changes the hardware makes by itself do not.

Self-Check

Tick each key point you covered in your answer.

Key point 1 Auto-prediction updates the mirror only for accesses made through the register model. Key point 2 The boot write is invisible to it, so the mirror stays at the reset value and the next mirror(UVM_CHECK) fails. Key point 3 Use explicit prediction instead: connect a uvm_reg_predictor to the bus monitor. Key point 4 The predictor converts every observed transfer with the adapter and updates the right register. Key point 5 Turn auto-prediction off, so each access is predicted once.

What Interviewers Listen For (Mid-Level)

A good mid-level answer names the invisible boot write as the cause. It draws the path: bus monitor, then predictor, then register model.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItCompare

Auto vs Explicit Register Prediction
WhyWhy Explicit Prediction Matters at SoC LevelL3 Senior
Why does explicit prediction matter more once the block sits inside an SoC?

Reveal the Model Answer

At SoC level, a CPU model, a DMA or a debug port may write the same registers through other paths. The block's register model never starts those writes. Only a predictor listening on the block's own bus sees them all. The same prediction setup then works unchanged at both levels.

Self-Check
Tick each key point you covered in your answer.
Key point 1 At SoC level, a CPU model, a DMA or a debug port may write the same registers through other paths. Key point 2 The block's register model never starts those writes. Key point 3 Only a predictor listening on the block's own bus sees them all. Key point 4 The same prediction setup then works unchanged at both levels.
- Lesson U13.3Predict from Observed Bus Traffic
- Lesson U12.2Vertical Reuse: A Block Environment Inside a Subsystem
What IfA Write to an Address the Map LacksL2 Mid-LevelL3 Senior
What if the predictor sees a bus write to an address that the register map does not contain?

Reveal the Model Answer

The predictor updates nothing. The uvm-core library reports it only as an info message at UVM_FULL verbosity, so a normal run prints nothing. That can hide a decode bug, or a register missing from the model. Raise the verbosity for that message in a check run, or count such writes yourself.

Self-Check
Tick each key point you covered in your answer.
Key point 1 The predictor updates nothing. Key point 2 The uvm-core library reports it only as an info message at UVM_FULL verbosity, so a normal run prints nothing. Key point 3 That can hide a decode bug, or a register missing from the model. Key point 4 Raise the verbosity for that message in a check run, or count such writes yourself.

Tool as Truth

"A write to an unknown address would show up as a UVM error."

The predictor reports REG_PREDICT_NOT_FOR_ME at UVM_FULL. At default verbosity it is not printed.

Source uvm-core 2020.3.1 (IEEE 1800.2 library) source, reg/uvm_reg_predictor.svh (REG_PREDICT_NOT_FOR_ME, UVM_FULL)
- Lesson U13.3Predict from Observed Bus Traffic
- Lesson U12.2Vertical Reuse: A Block Environment Inside a Subsystem
What IfPredicting from an Errored TransferL3 Senior
What if a register write ends with an error response, such as PSLVERR, and the register did not change?

Reveal the Model Answer

It depends on the adapter and the UVM version. In uvm-core, the predictor passes the status from bus2reg(), and the register skips a prediction marked UVM_NOT_OK. So bus2reg() must map the error to UVM_NOT_OK. The UVM Cookbook, written for UVM 1.1, says the status is ignored there. Older benches therefore filter errored transfers before the predictor.

Self-Check
Tick each key point you covered in your answer.
Key point 1 It depends on the adapter and the UVM version. Key point 2 In uvm-core, the predictor passes the status from bus2reg(), and the register skips a prediction marked UVM_NOT_OK. Key point 3 So bus2reg() must map the error to UVM_NOT_OK. Key point 4 The UVM Cookbook, written for UVM 1.1, says the status is ignored there. Key point 5 Older benches therefore filter errored transfers before the predictor.

Spec Misquote

"The predictor always ignores errors, so the mirror is always updated."

That was the UVM 1.1 behaviour the Cookbook describes. In uvm-core 2020.3.1, do_predict() skips a UVM_NOT_OK item with a warning.

Source uvm-core 2020.3.1 (IEEE 1800.2 library) source, reg/uvm_reg.svh (do_predict: "status UVM_NOT_OK; skip prediction")
- Lesson U13.3Predict from Observed Bus Traffic
Prove ItConnecting an Explicit PredictorL2 Mid-Level
Prove it: write the connect-phase code that sets up explicit prediction.
2:30

You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.

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Reveal the Model Answer

Give the map its sequencer and adapter, and turn auto-prediction off. Point the predictor at the map, so it can find a register by address. Give it the adapter, so it can convert bus items. Then connect the bus monitor's analysis port to the predictor's bus_in.
Four connections: sequencer and adapter, prediction off, map and adapter, monitor to predictor.
function void connect_phase(uvm_phase phase); regs.default_map.set_sequencer(apb.sqr, adapter); regs.default_map.set_auto_predict(0); // one prediction path only predictor.map = regs.default_map; // address -> register predictor.adapter = adapter; // bus item -> register operation apb.mon.ap.connect(predictor.bus_in); // every observed transfer endfunction

Self-Check
Tick each key point you covered in your answer.
Key point 1 Give the map its sequencer and adapter, and turn auto-prediction off. Key point 2 Point the predictor at the map, so it can find a register by address. Key point 3 Give it the adapter, so it can convert bus items. Key point 4 Then connect the bus monitor's analysis port to the predictor's bus_in.
Missed Corner

Connects the predictor to the driver instead of the monitor.

The driver sees only the model's own items, which is auto-prediction again. Other masters' writes still go unseen.

Source Verification Academy, UVM Cookbook, Registers: explicit prediction listens to the bus agent's monitor (PDF p337)
- Lesson U13.3Predict from Observed Bus Traffic
CompareWhen Auto-Prediction Is Good EnoughL2 Mid-Level
Compare the two modes. When is auto-prediction good enough?

Reveal the Model Answer

In a unit bench where the register model is the only master on the bus. It needs no monitor or predictor, so it is quick to set up. As soon as anything else can write the registers, switch to explicit prediction.

Self-Check
Tick each key point you covered in your answer.
Key point 1 In a unit bench where the register model is the only master on the bus. Key point 2 It needs no monitor or predictor, so it is quick to set up. Key point 3 As soon as anything else can write the registers, switch to explicit prediction.
- Lesson U13.2An APB Adapter and Frontdoor Access

What People Get Wrong

Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.

Misconception

"With auto-prediction on, the mirror follows every write to the DUT."

It hooks only the register model's own accesses. The twin's boot write goes straight to the sequencer, so the mirror stays at 1 and the check fails.

Run It

A raw APB boot write, then a mirror check, with auto-prediction on and no predictor.

RUNVerilator + UVM 2020.3.1 · simulator service

Edit the code, then run it

Expected among the UVM messages: 25 ns APB write addr=0 data=a5 30 ns after the boot write: mirrored=1 FAIL: auto-prediction saw only model calls, so the raw write left a stale mirror of 1 UVM_ERROR : 1

`timescale 1ns/1ns
`include "uvm_macros.svh"
import uvm_pkg::*;

// The incrementer's register slice on a small APB bus.
interface apb_if (input logic clk);
  logic        psel = 0, penable = 0, pwrite = 0;
  logic [31:0] paddr = 0, pwdata = 0;
  logic [31:0] prdata;
  logic        pready;
endinterface

// CTRL at address 0 (8 bits, read-write); every access completes at once.
module incr_csr (apb_if bus);
  logic [7:0] ctrl = 8'h01;
  assign bus.pready = 1;
  assign bus.prdata = (bus.paddr == 0) ? {24'b0, ctrl} : 32'b0;
  always @(posedge bus.clk)
    if (bus.psel && bus.penable && bus.pwrite && bus.paddr == 0)
      ctrl <= bus.pwdata[7:0];
endmodule

class apb_item extends uvm_sequence_item;
  `uvm_object_utils(apb_item)
  bit          write;
  bit   [31:0] addr, data;
  function new(string name = "apb_item"); super.new(name); endfunction
endclass

class ctrl_reg extends uvm_reg;
  `uvm_object_utils(ctrl_reg)
  rand uvm_reg_field mode;
  function new(string name = "ctrl_reg"); super.new(name, 32, UVM_NO_COVERAGE); endfunction
  function void build();
    mode = uvm_reg_field::type_id::create("mode");
    mode.configure(this, 8, 0, "RW", 0, 8'h01, 1, 1, 0);
  endfunction
endclass

class incr_regs extends uvm_reg_block;
  `uvm_object_utils(incr_regs)
  rand ctrl_reg ctrl;
  function new(string name = "incr_regs"); super.new(name, UVM_NO_COVERAGE); endfunction
  function void build();
    ctrl = ctrl_reg::type_id::create("ctrl");
    ctrl.configure(this);
    ctrl.build();
    default_map = create_map("map", 'h0, 4, UVM_LITTLE_ENDIAN);
    default_map.add_reg(ctrl, 'h0, "RW");
    lock_model();
  endfunction
endclass

// Translates between a register operation and an APB item.
class apb_adapter extends uvm_reg_adapter;
  `uvm_object_utils(apb_adapter)
  function new(string name = "apb_adapter");
    super.new(name);
    supports_byte_enable = 0;
    provides_responses   = 0;   // the driver writes read data into the request itself
  endfunction
  virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
    apb_item t = apb_item::type_id::create("t");
    t.write = (rw.kind inside {UVM_WRITE, UVM_BURST_WRITE});
    t.addr  = rw.addr;
    t.data  = rw.data;
    return t;
  endfunction
  virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);
    apb_item t;
    if (!$cast(t, bus_item)) `uvm_fatal("NOTAPB", "bus2reg needs an apb_item")
    rw.kind   = t.write ? UVM_WRITE : UVM_READ;
    rw.addr   = t.addr;
    rw.data   = t.data;
    rw.status = UVM_IS_OK;
  endfunction
endclass

class apb_driver extends uvm_driver #(apb_item);
  `uvm_component_utils(apb_driver)
  virtual apb_if vif;
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
  task run_phase(uvm_phase phase);
    forever begin
      seq_item_port.get_next_item(req);
      @(negedge vif.clk);                       // setup phase
      vif.psel <= 1; vif.penable <= 0;
      vif.pwrite <= req.write; vif.paddr <= req.addr; vif.pwdata <= req.data;
      @(negedge vif.clk);                       // access phase
      vif.penable <= 1;
      do @(posedge vif.clk); while (!vif.pready);
      if (!req.write) req.data = vif.prdata;    // read data goes back in the request
      $display("%3d ns  APB %s addr=%0h data=%h", $time,
               req.write ? "write" : "read ", req.addr, req.data[7:0]);
      @(negedge vif.clk);
      vif.psel <= 0; vif.penable <= 0;
      seq_item_port.item_done();
    end
  endtask
endclass

// Watches the pins and publishes every completed transfer.
class apb_monitor extends uvm_monitor;
  `uvm_component_utils(apb_monitor)
  virtual apb_if vif;
  uvm_analysis_port #(apb_item) ap;
  function new(string name, uvm_component parent);
    super.new(name, parent);
    ap = new("ap", this);
  endfunction
  task run_phase(uvm_phase phase);
    forever begin
      @(posedge vif.clk);
      if (vif.psel && vif.penable && vif.pready) begin
        apb_item t = apb_item::type_id::create("t");
        t.write = vif.pwrite;
        t.addr  = vif.paddr;
        t.data  = vif.pwrite ? vif.pwdata : vif.prdata;
        ap.write(t);
      end
    end
  endtask
endclass

// A boot sequence that writes CTRL on the bus without using the register model.
class boot_write extends uvm_sequence #(apb_item);
  `uvm_object_utils(boot_write)
  function new(string name = "boot_write"); super.new(name); endfunction
  task body();
    apb_item t = apb_item::type_id::create("t");
    start_item(t);
    t.write = 1; t.addr = 0; t.data = 'ha5;
    finish_item(t);
  endtask
endclass

class auto_test extends uvm_test;
  `uvm_component_utils(auto_test)
  incr_regs                 regs;
  apb_adapter               adapter;
  apb_driver                drv;
  uvm_sequencer #(apb_item) sqr;
  function new(string name, uvm_component parent); super.new(name, parent); endfunction
  function void build_phase(uvm_phase phase);
    regs = incr_regs::type_id::create("regs");
    regs.build();
    adapter = apb_adapter::type_id::create("adapter");
    sqr = uvm_sequencer #(apb_item)::type_id::create("sqr", this);
    drv = apb_driver::type_id::create("drv", this);
    if (!uvm_config_db #(virtual apb_if)::get(this, "", "vif", drv.vif))
      `uvm_fatal("NOVIF", "no virtual interface")
  endfunction
  function void connect_phase(uvm_phase phase);
    drv.seq_item_port.connect(sqr.seq_item_export);
    regs.default_map.set_sequencer(sqr, adapter);
    // The belief: with auto-prediction on, the mirror follows every write to the DUT.
    regs.default_map.set_auto_predict(1);
  endfunction
  task run_phase(uvm_phase phase);
    uvm_status_e status;
    bit [7:0]    seen;
    boot_write   boot = boot_write::type_id::create("boot");
    phase.raise_objection(this);
    regs.reset();
    boot.start(sqr);                       // a raw APB write of a5, not through the model
    seen = regs.ctrl.get_mirrored_value();
    $display("%3d ns  after the boot write: mirrored=%0h", $time, seen);
    regs.ctrl.mirror(status, UVM_CHECK);   // read the DUT and compare with the mirror
    if (seen != 8'ha5)
      $display("FAIL: auto-prediction saw only model calls, so the raw write left a stale mirror of 1");
    phase.drop_objection(this);
  endtask
endclass

module tb;
  bit clk;
  always #5 clk = ~clk;
  apb_if   bus (clk);
  incr_csr dut (bus);
  initial begin
    uvm_config_db #(virtual apb_if)::set(null, "uvm_test_top", "vif", bus);
    run_test("auto_test");
  end
endmodule

Missed Corner

"Keep auto-prediction on as well as the predictor, to be safe."

Each model access is then predicted twice. For a toggle-on-write field (W1T), two predictions toggle the mirror twice, so it ends wrong.

Source uvm-core 2020.3.1 (IEEE 1800.2 library) source, reg/uvm_reg_field.svh (W1T prediction: current value XOR written value)

Wrong Altitude

"Explicit prediction is the newer, better API, so always use it."

It costs a monitor and a predictor. In a unit bench where the model is the only bus master, auto-prediction is enough and simpler.

Find Your Next Track

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Prepare to Explain Your Thinking

An Idea to Try? Pick a Tool.

Auto vs Explicit Register Prediction

Your Answer

Self-Check

What Interviewers Listen For (Mid-Level)

What Interviewers Listen For (Senior)

Cross-Questions

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What People Get Wrong

Learn It, Then Prove It

The Question

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What Interviewers Listen For (Mid-Level)

What Interviewers Listen For (Senior)

Cross-Questions

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What People Get Wrong

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