Heavy Buses: Drive, Buffers, Series Resistors and Wiring

Read the Table 10 I/O stage, pick a remedy for a bus above its capacitance limit and compute its fmax with Eq. 3, and size series resistors and pull-ups from the noise margins.

Lesson: P8.13
Time: 35 min
Runs on: ngspice
Check: 4 questions

A controller board ran sensors along a cable that measured 800 pF. On 1 kΩ pull-ups its rise was 678 ns, so Fast-mode parts could not run at 400 kHz. The fix was not one resistor: it was a choice between slower clocks, stronger drivers and a buffer.

TransientThree Ways to Carry 800 pFOne 400 pF segment on 1 kΩ, the whole 800 pF bus on 1 kΩ, and 800 pF on 330 Ω with Fm+ drive, at 3.3 V. Each driver lets go at 0 and pulls at 2.5 µs.

400 pF segment, 1 kΩ
800 pF, 1 kΩ
800 pF, 330 Ω, Fm+

Time 317.8 ns400 pF segment, 1 kΩ = 1.809 V · 800 pF, 1 kΩ = 1.082 V · 800 pF, 330 Ω, Fm+ = 2.31 V
330 Ω with 20 mA parts: a 224 ns rise, inside Fast-mode even at 800 pF.
Time 481.6 ns400 pF segment, 1 kΩ = 2.31 V · 800 pF, 1 kΩ = 1.493 V · 800 pF, 330 Ω, Fm+ = 2.768 V
One 400 pF segment on 1 kΩ: 339 ns, still over Fast-mode's 300 ns at 3.3 V.
Time 963.2 ns400 pF segment, 1 kΩ = 3.003 V · 800 pF, 1 kΩ = 2.31 V · 800 pF, 330 Ω, Fm+ = 3.214 V
The whole 800 pF on 1 kΩ: 678 ns, legal only at Standard-mode speed.

Read the plot as a table

Time	400 pF segment, 1 kΩ	800 pF, 1 kΩ	800 pF, 330 Ω, Fm+
317.8 ns	1.809 V	1.082 V	2.31 V
481.6 ns	2.31 V	1.493 V	2.768 V
500 ns	2.355 V	1.534 V	2.803 V
963.2 ns	3.003 V	2.31 V	3.214 V
1 µs	3.029 V	2.355 V	3.225 V
1.5 µs	3.222 V	2.794 V	3.289 V
2 µs	3.278 V	3.029 V	3.298 V
2.5 µs	3.294 V	3.155 V	3.3 V
3 µs	387.4 mV	400.9 mV	188.6 mV

Simulated on the Analog engine (ngspice 42). A driver is a switch of VOL / IOL: 133 Ω for 3 mA parts, 20 Ω for 20 mA parts. A 1 kΩ pull-up is just above Rp(min) = 967 Ω for 3 mA; 330 Ω is above 145 Ω for 20 mA.

The I/O Stage

Table 10 describes the pins: input thresholds, the sink current at 0.4 V, the output fall, the spike filter, the leakage and the capacitance (§6.1). Table 11 then describes the bus those pins make. Each row below returns somewhere on this page.

Table 10 row	Sm	Fm	Fm+	Where it matters
VIL / VIH	0.3 / 0.7 VDD	0.3 / 0.7 VDD	0.3 / 0.7 VDD	every rise, fall and noise margin is measured to these
Vhys (min)	–	0.05 VDD	0.05 VDD	Schmitt inputs ride out slow, noisy edges
VOL at 3 mA, VDD > 2 V (max)	0.4 V	0.4 V	0.4 V	Rp(min) (§7.1); the LOW that series resistors add to (§7.3)
IOL at VOL = 0.4 V (min)	3 mA	3 mA	20 mA	more drive allows more capacitance (§7.2.2)
IOL at VOL = 0.6 V (min)	–	6 mA	–	note 4: needed to drive 400 pF at 400 kHz
tof, output fall (max)	250 ns	250 ns	120 ns	the bus tf may be 300 ns, which leaves room for Rs (note 5); not in Fm+ (note 7)
tSP, spike filter	–	0 to 50 ns	0 to 50 ns	glitches shorter than this are ignored
Ii, input current (each pin)	±10 µA	±10 µA	±10 µA	Rp(max) (§7.4)
Ci, pin capacitance (max)	10 pF	10 pF	10 pF	part of Cb before any wire is added

UM10204 Table 10 (§6.1). The tof minimum in Fm and Fm+ is 20 ns × VDD / 5.5 V, for compatibility with Fast-mode. Note 9: an Fm or Fm+ device with VDD off must not hold the lines. Note 1: some legacy Sm parts used fixed 1.5 V and 3 V input levels.

Above the Capacitance Limit

The capacitance limit keeps the rise short enough for the rated fSCL (§7.2). Over it, there are four ways out: a slower clock, stronger drivers, a buffer or switch that splits the bus, or the switched pull-up of P8.7 (§7.2.1 to §7.2.4).

Eq. 3 gives the highest clock for a real bus: fmax = 1 / (tLOW(min) + tHIGH(min) + tr + tf), with the minima of the slowest device and the measured edges (§7.2.1). With stronger drivers, repeat it with the new Rp, tr and tf (§7.2.2).

Remedy	Load per segment	Rise / fall (measured)	Eq. 3 fmax	Result
None: Fm parts, 1 kΩ	800 pF	678 / 109 ns	372 kHz (Fm minima)	rise is over Fast-mode's 300 ns
Reduced fSCL (§7.2.1)	800 pF	the same	105 kHz (Sm minima)	run at 100 kHz; the rise is inside Sm's 1000 ns
Higher drive (§7.2.2): Fm+ parts, 330 Ω	800 pF	224 / 15 ns	1002 kHz (Fm+ minima)	capped at 1000 kHz (Table 11); 800 pF is still over the 550 pF Fm+ limit
Buffer (§7.2.3): two segments, 1 kΩ each	400 pF	339 / 54 ns	436 kHz before the buffer delay	still over 300 ns: at 3.3 V no 3 mA pull-up suits 400 pF (P8.7)

Rise and fall from the plot above; fmax from Eq. 3 with the device minima of Table 11 for tLOW and tHIGH. Real parts are slower than their minima (§7.2.1), and a very long bus also adds time of flight. A buffer adds its own delay and an extra transition to every edge.

Splitting a Bus with a BufferEach segment may carry the full capacitance limit; the buffer joins them.

Twice the load
Each side has its own pull-ups and its own capacitance budget, so the whole bus can carry twice the limit.
The price
Every edge now crosses the buffer, which lowers the highest usable fSCL and may bring its own VIL and VOL rules.

Read the diagram as text

Segment 1: controllers and targets, up to 400 pF
Buffer: delay plus a transition per edge
Segment 2: controllers and targets, up to 400 pF
VDD1 and VDD2: may differ with some buffers

Segment 1 → Buffer: SDA, SCL
Buffer → Segment 2: SDA, SCL
VDD1 and VDD2 → Buffer

After UM10204 Fig. 43 and §7.2.3. Multiplexers and switches split a bus the same way.

Series Protection Resistors

A resistor of a few hundred ohms in each line, at each device, protects the pins from high-voltage spikes (§7.3). It also sits in the path of every LOW. The bus LOW rises by Rs times the pull-up current, and Table 11 wants 0.1 VDD of margin below VIL.

TransientThe LOW Behind a Series Resistor5 V, Rp 4 kΩ, 100 pF. The driver's pin is a switch to its worst-case 0.4 V and pulls at 3 µs through Rs.

Rs = 0
Rs = 300 Ω
Rs = 600 Ω
Rs = 1 kΩ

Time 3.5 µsRs = 0 = 401.2 mV · Rs = 300 Ω = 721.9 mV · Rs = 600 Ω = 1.001 V · Rs = 1 kΩ = 1.328 V
The LOW settles at 0.40 V with no Rs, 0.72 V with 300 Ω and 1.00 V with 600 Ω: right at the 0.1 VDD margin.
Time 3.8 µsRs = 0 = 401.2 mV · Rs = 300 Ω = 721.9 mV · Rs = 600 Ω = 1.001 V · Rs = 1 kΩ = 1.321 V
With 1 kΩ it settles at 1.32 V. A receiver still reads LOW, but with less noise margin than Table 11 requires.

Read the plot as a table

Time	Rs = 0	Rs = 300 Ω	Rs = 600 Ω	Rs = 1 kΩ
500 ns	3.567 V	3.567 V	3.567 V	3.567 V
1 µs	4.59 V	4.59 V	4.59 V	4.59 V
1.5 µs	4.882 V	4.882 V	4.882 V	4.882 V
2 µs	4.966 V	4.966 V	4.966 V	4.966 V
2.5 µs	4.99 V	4.99 V	4.99 V	4.99 V
3 µs	4.997 V	4.997 V	4.997 V	4.997 V
3.5 µs	401.2 mV	721.9 mV	1.001 V	1.328 V
3.8 µs	401.2 mV	721.9 mV	1.001 V	1.321 V
4 µs	401.2 mV	721.9 mV	1.001 V	1.321 V

Simulated on the Analog engine (ngspice 42). The same pull-up is seen on every run, so the rises overlap; only the LOW and the fall differ.

Rs	LOW (measured)	Margin below VIL	Fall 70 to 30 % (measured)
0	0.401 V	1.099 V (needs 0.5 V)	switch only
300 Ω	0.722 V	0.778 V (needs 0.5 V)	35.6 ns
600 Ω	1.001 V	0.499 V (needs 0.5 V)	84.2 ns
1.00 kΩ	1.321 V	0.179 V (needs 0.5 V)	200.0 ns

Measured. Solving for the limit: Rs(max) = (0.2 VDD − 0.4 V) × Rp / (0.8 VDD). At Rp = 4 kΩ that is 200 Ω at 2.5 V, 600 Ω at 5 V and 800 Ω at 10 V; Figure 46's curves pass close to these three points. Series resistors also slow the fall.

Leakage Sets the Largest Pull-Up

Each pin may leak up to 10 µA while HIGH (§7.4, Table 10). All of it flows through Rp, so the HIGH sags by the total times Rp. Table 11 wants 0.2 VDD of margin above VIH, so the HIGH must stay above 0.9 VDD.

TransientLeakage Pulls the HIGH Down3.3 V, Rp 4.7 kΩ, 100 pF, with no leakage and with 10 and 20 inputs at the 10 µA maximum.

no leakage
100 µA (10 inputs)
200 µA (20 inputs)

Time 3 µsno leakage = 3.294 V · 100 µA (10 inputs) = 2.825 V · 200 µA (20 inputs) = 2.356 V
With 100 µA the HIGH stops at 2.83 V, under the 2.97 V that keeps the 0.2 VDD margin.
Time 3.8 µsno leakage = 3.299 V · 100 µA (10 inputs) = 2.829 V · 200 µA (20 inputs) = 2.359 V
With 200 µA it stops at 2.36 V, barely above VIH, and the rise takes 1556 ns instead of 398.

Read the plot as a table

Time	no leakage	100 µA (10 inputs)	200 µA (20 inputs)
500 ns	2.161 V	1.853 V	1.545 V
1 µs	2.907 V	2.493 V	2.079 V
1.5 µs	3.164 V	2.714 V	2.263 V
2 µs	3.253 V	2.79 V	2.327 V
2.5 µs	3.284 V	2.816 V	2.348 V
3 µs	3.294 V	2.825 V	2.356 V
3.5 µs	3.298 V	2.828 V	2.359 V
3.8 µs	3.299 V	2.829 V	2.359 V
4 µs	3.299 V	2.829 V	2.36 V

Simulated on the Analog engine (ngspice 42). The drop is the total leakage times Rp. Keeping it under 0.1 VDD gives Rp(max) = 0.1 VDD / I: 3.30 kΩ for 100 µA and 1.65 kΩ for 200 µA at 3.3 V. This is the page's arithmetic; Figure 47 is the specification's chart of the same limit, so size from the chart.

Wiring the Bus

Keep SDA and SCL apart and give them equal loads (§7.5). The patterns below put a supply line between them.

Bus lines	Pattern	Why
PCB or ribbon cable over 10 cm, with VDD and VSS	SDA, VDD, VSS, SCL	SDA and SCL are kept apart, and both see the same load
The same, with VSS only	SDA, VSS, SCL	the same reasons
PCB with a VSS and/or VDD plane	the VSS and VDD lines can be left out	the plane takes their place
Twisted pairs	each line twisted with VSS; or SCL with VSS and SDA with VDD	with VDD returns, decouple VDD to VSS at both ends
Shielded cable	shield to VSS	the cable still needs low SDA-to-SCL coupling

UM10204 §7.5. The lines are most open to crosstalk and interference while HIGH, when only the pull-up holds them.

Try It

Four copies of one bus at 5 V: Rp 4 kΩ, 100 pF, and a driver behind Rs = 0, 300, 600 and 1000 Ω. The driver is a switch to 0.4 V, the worst-case VOL. Each copy prints its rise, its settled LOW and its fall.

Change Rp from 4000 to 2000 and run again: the pull-up current doubles, so every Rs costs twice the LOW.

SPICEngspice 42 · simulator service

Edit the netlist, then run it

Expected measurements: low_rs0 ≈ 0.4011509 low_rs300 ≈ 0.7219251 low_rs600 ≈ 1.00087 low_rs1000 ≈ 1.320784

Check Yourself

Predict the outputVDD 5 V, Rp 4 kΩ, and a driver whose pin sits at its worst-case 0.4 V behind Rs = 600 Ω. The run prints the bus LOW. Type the line meas prints (format: low = 7.219251e-01).

Series resistor at the LOW level (UM10204 Rev 7 section 7.3)
Vdd vdd 0 5
Vol pin 0 0.4
Rp vdd bus 4k
Rs bus pin 600
.tran 1n 1u
.meas tran low FIND v(bus) AT=0.5u
.end

ConceptAn 800 pF bus of 3.3 V parts must run at 400 kHz. Which single change can make that work?

A buffer that splits it into two 400 pF segments on 1 kΩ eachA larger pull-up, which lowers the current each device must sinkFm+ parts with a 330 Ω pull-up, so the edges are fast enoughEq. 3 with Fast-mode minima, which allows a little over 400 kHz

ConceptFigure 46 allows a larger Rs at a higher VDD for the same Rp. Why?

A higher VDD lowers the pull-up current through RsThe spike filter is wider at a higher supply voltageHigher-voltage parts have stronger output transistorsThe 0.1 VDD margin scales with VDD; the 0.4 V VOL does not

ConceptA 30 cm ribbon cable carries SDA, SCL, VDD and VSS. Which order does §7.5 give?

SDA, VDD, VSS, SCLVDD, SDA, SCL, VSSSDA, SCL, VDD, VSSSCL, SDA, VSS, VDD

Remember

Table 10 sets the pins: 0.3 and 0.7 VDD thresholds, 0.4 V at 3 mA (20 mA for Fm+), 10 µA leakage and 10 pF each.
Over the capacitance limit: slow the clock, use stronger drivers, split the bus, or switch the pull-up; Eq. 3 gives the real fmax.
A series resistor raises the LOW by Rs times the pull-up current; the 0.1 VDD margin below VIL caps it (Figure 46).
Leakage lowers the HIGH by the total current times Rp; the 0.2 VDD margin above VIH caps Rp (Figure 47).
Over 10 cm, run a supply line between SDA and SCL, or twist each with a return.

Practice

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Heavy Buses: Drive, Buffers, Series Resistors and Wiring

The I/O Stage

Above the Capacitance Limit

Series Protection Resistors

Leakage Sets the Largest Pull-Up

Wiring the Bus

Try It

Check Yourself

Remember

Practice