Clock Domain Crossing Interview Questions

Each bit's synchronizer can resolve on a different destination edge, so the destination can see a mix of old and new bits. Instead, hold the data stable and synchronize only a control signal. That can be a valid level, a toggle, or a request and acknowledge. For counters that step by one, Gray-code the value. For a stream of words, use an asynchronous FIFO.

The bits reach their flops at slightly different times, because wires and gates differ. If a destination edge falls between those times, one flop sees the new value and another the old. A flop that goes metastable can also resolve either way. Nothing ties one bit's synchronizer to another's.

With one flop, logic reads its output in the same cycle that it might be metastable. Only the slack left after that logic is available for settling. Different gates can even read the same hanging value as different levels. The second flop isolates that settling from all other logic, and gives it about a full period.

MTBF grows exponentially with settling time, so a third flop adds a full period and multiplies MTBF. Compute MTBF from the flop's library data at the worst corner. Add stages until it is far beyond the product lifetime. Each stage also adds one cycle of latency to the crossing.

With held data, the source holds the word while an enable crosses, so one word takes several destination cycles. It is small and suits configuration or occasional events. An asynchronous FIFO writes a word every source cycle and crosses only Gray-coded pointers. It suits streams, at the cost of memory and pointer logic.

Gray code changes one bit per step, so a value caught mid-change is either the old or the new one. It suits counters that move by one, such as FIFO pointers. A handshake holds any data stable while a synchronized request crosses and an acknowledge comes back. It carries any value, but takes several cycles per transfer. Choose Gray for streaming pointers, and a handshake or FIFO for occasional wide data.

Then the crossing is synchronous, and STA can time it, because the edges have a known relation. No synchronizer is needed if the paths meet timing on the tightest edge pair. Declare the clocks as related, never as asynchronous groups. If the relation is not guaranteed, for example after a clock switch, treat it as asynchronous.

The sender puts the word on data, holds it, and raises req. The receiver synchronizes req, takes data when the synchronized req rises, and raises ack. The sender synchronizes ack, then drops req. The receiver sees req low and drops ack. The data needs no synchronizer, because it is stable long before the receiver reads it.

In a two-phase handshake, every toggle of req is a new request and every toggle of ack answers it. So each word needs one round trip instead of two. The cost is edge detection on both sides, an XOR of two flops. Four-phase uses plain levels and is easier to read and check.

No. Each word waits for two synchronizer delays in each direction, several cycles of each clock. In the run, three words took about 330 ns with 10 ns and 14 ns clocks. A stream needs an asynchronous FIFO. It crosses only the Gray-coded pointers, and words flow every cycle while it is neither full nor empty.

The receiver clears ack and forgets the word, while the sender still holds req high. When the receiver leaves reset, it sees req high again and may take the same word twice. It may also miss the edge entirely. Each domain needs its own reset synchronizer, and a crossing needs a rule for what happens when one side is in reset.

Each one-cycle source pulse flips tog, a level that stays put until the next pulse. Two destination flops synchronize the level, and the XOR of the last two flops gives one destination pulse per change. Back-to-back pulses flip tog twice before the destination samples it. Then the destination sees no change and both pulses vanish. Pulses must be spaced by a few destination periods.

The pulse can rise and fall between two destination edges and never be sampled. One fix is to hold the signal for at least about 1.5 destination periods. Another is to turn the pulse into a toggle, synchronize the level, and turn each change back into a pulse. For events that must not be lost or merged, use a handshake.

The toggle is open loop. The source never learns whether the event arrived, so a design rule must keep events far enough apart. A handshake is closed loop. The source waits for the acknowledge, so it cannot send too fast, but each event costs a round trip. Choose the toggle when the spacing is guaranteed, and the handshake when it is not.

d1 is the flop that samples the asynchronous toggle, so it is the one that can go metastable. Feeding it to the XOR lets an unsettled value reach logic. Take the edge from two flops after the synchronizer, such as d2 ^ d3.

Combinational logic in front of the first flop can glitch, and the destination may catch the glitch. Synchronizing one signal in two places lets the two copies resolve differently. Signals synchronized separately and then combined again lose any timing relationship between them. Logic between the two flops eats the settling time.

Each toggle level must last long enough for the destination to sample it reliably. That is about 1.5 destination periods, so three destination edges see it. Add the synchronizer depth and convert to source cycles at the slowest destination clock. Check the rule with an assertion on the source side.

Start with a written clock and reset spec: every clock, which are related, and each reset's domain. Run structural CDC checks until every crossing has an approved scheme, with no logic before synchronizers and no reconvergence. Turn each scheme's rule into an assertion, run it in formal and simulation, and add metastability injection. Bound the Gray buses with max-delay constraints. Done means zero open violations, and every waiver reviewed with a named owner.

A false path tells STA to ignore the bus, so place and route may stretch one bit far longer than another. Gray code only promises one change per step at the source. If the skew exceeds a destination period, two steps can overlap at the receiver. A max-delay bound of about one period keeps the bits together, and STA then checks it.

No. set_clock_groups -asynchronous acts as false paths between the two clocks. In SDC precedence a false path outranks set_max_delay, so the pointer bound is dropped. This was confirmed on OpenSTA 3.1.0. Write the bound with path-level exceptions, and check the report to show it is applied.

A synchronizer model that randomly adds a cycle of delay per bit shows how the design behaves when a crossing resolves late. It exposes logic that assumes an exact latency, and reconvergence that only fails with skew. It cannot prove absence: it finds only what the tests happen to reach.

Each domain gets its own reset synchronizer: assert at once, release on two edges of its own clock. Then the domains leave reset at different times. Every crossing needs a rule for that window, such as a ready flag from the receiver. A reset in one domain must not corrupt a flop in another domain that is mid-capture.

A waiver records an assumption, such as "this bus is static during operation". The tool stops checking, but nothing enforces the assumption. Later, software writes the register while traffic runs, or an RTL change adds a new path under the old waiver. Waivers need a stated assumption, an owner and a re-check after every change.

Then it can cross without a synchronizer, but only if that rule really holds. Write it down as a protocol: the block is idle or in reset when the register changes. Check it with an assertion in simulation and formal. Tell the software team, because they are the ones who could break it.

Start with structural analysis: define the clocks and their relationships. Then let the tool find every crossing and check that each has the right synchronizer for its type. Next comes protocol checking: each scheme's rules, such as hold times and Gray steps, become assertions in formal and simulation. Add reconvergence checks and reviewed waivers. Use metastability injection in simulation to expose designs that assume exact timing.