Timing and Reset Interview Questions

A posedge counter that goes 0, 1, 2 can only make edges at whole input periods. So make a pulse q_pos that is high for one period in three. Copy it with a flop on the falling edge, so q_neg is the same pulse half a period later. Then q_pos | q_neg is high for 1.5 periods and low for 1.5. That is 50%, as long as the input clock is 50%.

An even divider toggles one flop every N/2 input periods, so its output is 50% with rising edges only. Divide by 2 is one flop with q <= ~q. Divide by 4 toggles every second edge. An odd ratio cannot split into equal halves of whole periods, so it needs the falling edge too.

The output must be high for 1.5 input periods. Rising edges come only at whole periods, so no rising-edge logic can end a pulse halfway. The falling edge is the only other edge that the input clock gives you.

The falling-edge flop now delays the pulse by the input's high time, 4 ns instead of 5. So the output is high 14 ns and low 16 ns. The 50% divide-by-3 only promises 50% when the input is 50%.

STA sees flops whose clock pin comes from logic, not from a defined clock. It reports them as unclocked and does not time their paths. Declare the output with create_generated_clock, or better, keep one clock and use an enable. The divider flops also add delay that clock-tree tools must balance.

A clock made by logic is a new clock domain with its own skew and delay. STA must be told about it, and clock-tree tools must balance it. A plain mux between clocks can cut a pulse short when the select changes, and a short pulse can break flops. Prefer one clock with an enable. If a switch is truly needed, use a glitch-free switch or the library cell.

STA times paths from clocks it knows. A divider's output is a flop output, so STA does not treat it as a clock unless told. create_generated_clock names it, gives its ratio to the master and lets the tool add the divider delay to the clock latency.

With an enable, the logic keeps the main clock and updates only when a one-cycle tick is high. There is one clock tree, no crossing, and STA times it normally. The cost is the enable logic and some clock power. Clock gating with a library cell can remove most of that power.

A clock controller makes the clocks: PLLs, dividers, glitch-free switches and gating cells taken from the library. It ships with its constraints. Block RTL receives clocks and uses enables or library gating cells. It never builds clocks from its own logic. Then STA, clock-tree synthesis and CDC checks all start from one list of clocks.

The old side turns off on its own falling edge. The new side turns on only at a falling edge of the new clock. If that clock is stopped, it never turns on, so the output stays low. The system must start the new clock first, or use a switch with a fallback.

A synchronous reset is sampled at the clock edge like data. So it needs a running clock and a pulse that covers an edge. An asynchronous reset acts at once through the flop's reset pin, with no clock. Its assertion is easy; its release is the hard part, because it must meet recovery and removal times. Many ASICs use asynchronous assertion with a synchronized release.

Recovery time is how long before a clock edge the reset must be released. Removal time is how long after the edge it must stay asserted. They are the setup and hold of the reset pin. If the release lands inside that window, the flop may go metastable or leave reset one cycle late.

They now differ by one count forever, and nothing brings them back together. The cause is a raw asynchronous release. It reached one counter before an edge and the other just after it. A reset synchronizer releases both on the same edge, because its output changes only at a clock edge.

A synchronous reset is extra logic in front of D, such as an AND or a mux. Some libraries have flops with a synchronous reset input instead. It sits on the data path, so it can touch timing. In return, it filters short glitches on the reset line, and its release is just data, timed like any other path.

Use two flops with an asynchronous reset pin, both driven by the incoming reset. The first flop's D is tied to 1, and the second flop takes the first one's output. Reset clears both at once, with no clock. On release, a 1 moves through the two flops, so rst_n rises on the second edge. Only the first flop can go metastable, and the second gives it a cycle to settle.

The reset already reaches both flops through their reset pins, so D only has to describe the release. With D tied to 1, the only change D ever passes is "leave reset", one edge at a time. The input reset never enters a data path, which keeps it away from any combinational logic.

No. Each clock domain needs its own synchronizer, clocked by that domain's clock. A release synchronized to one clock is still asynchronous to the others. The domains then leave reset at different times. So the design must tolerate any release order, or sequence the releases on purpose.

Write the order into the spec, based on who talks to whom. A receiver should be out of reset before its sender can send, or the sender must wait for a "ready" from it. A small reset controller can release domains in steps, with handshakes through synchronizers. Verification then runs every release order the controller allows.

A fully synchronous scheme needs a running clock before reset takes effect. The reset must also last long enough to be sampled. In exchange, reset is ordinary data for timing and is filtered against glitches. The asynchronous-assert scheme resets with no clock, which matters at power-up and when clocks are gated. Many teams choose it for that reason.

Start with the goals: a known state after reset, a safe release, and no wasted area. Then give the scheme: asynchronous assert, a synchronizer per clock domain, and the release order. Reset every control flop: states, valid bits, counters and pointers. Datapath flops can skip reset when a reset valid bit guards them. Close with how you verified it, including reset in the middle of traffic.

Nothing reads the data until the valid bit says it is good, and the valid bit is reset to 0. The first valid beat loads real data into the flops at the same edge. Flops without reset pins are smaller and need no reset wiring. The rule breaks if any logic uses the data without checking valid.

Any logic that reads the data without checking valid. A debug counter or a parity check on the raw data are typical. After reset those flops hold unknown values, so the new logic sees X in simulation and random values in silicon. Guard every reader with valid.

The data is not reset, but it sits in the else of the reset if. So out_data must hold its value while reset is asserted. Synthesis adds that hold as an enable. On this flow the 8 data flops became enabled flops with rst_n as the enable. Put unreset flops in their own always_ff, without the reset in the list.

On many FPGAs, yes: the bitstream loads flops with their initial values at power-up. On an ASIC, no. Flops power up unknown, and the initial value exists only in simulation. An ASIC block needs a reset, and it then works the same on both targets.

When the soft reset asserts, its flops change at once, at no fixed time relative to the clock. A flop that is not in reset may sample one of them at that moment. Even on one clock, that path now behaves like an asynchronous crossing. Fix it by holding the receiver too, or by gating the path while the soft reset is active.

Setup time is how long D must be stable before the clock edge. Hold time is how long it must stay stable after the edge. Setup: clock-to-Q plus the slowest logic plus setup must fit in one period. Hold: clock-to-Q plus the fastest logic must be at least the hold time. The period appears only in the setup check. So a faster clock can break setup, but the clock speed never changes hold.

Hold is a race inside one clock edge. The same edge launches new data from the first flop and captures old data in the second flop. If the new data arrives before the hold time ends, it replaces the old value. Both events hang off the same edge, so the time to the next edge never enters.

The setup check moves one capture edge later, and by default the hold check moves with it. Hold is then checked one edge after launch, which is almost always a false violation. The usual pair is -setup 2 with -hold 1, which moves hold back to the launch edge.

Setup is fixed by making the slow path faster or giving it more time. Options are a faster cell or a restructured expression, a pipeline register, or a slower clock. Hold is fixed by making the fast path slower, usually with delay cells near the capture flop. Hold must be fixed at every corner, because a chip with a hold violation fails at any clock speed.

RTL flops and gates have zero delay, and they have no setup or hold windows. Data is always ready at the next edge, however short the period. Timing is checked by static timing analysis on the netlist, using library delays. Gate-level simulation with delays can also show it, but it is slower and covers fewer paths.

If the data arrives well after the edge, the flop simply keeps the old value, and the logic computes with stale data. If it changes inside the setup window, the flop can go metastable and settle late to either value. The run shows both: wrong values at 4000 ps and window hits at 5000 ps.

With one flop, logic reads its output in the same cycle that it might be metastable. Only the slack left after that logic is available for settling. Different gates can even read the same hanging value as different levels. The second flop isolates that settling from all other logic, and gives it about a full period.

MTBF grows exponentially with settling time, so a third flop adds a full period and multiplies MTBF. Compute MTBF from the flop's library data at the worst corner. Add stages until it is far beyond the product lifetime. Each stage also adds one cycle of latency to the crossing.

First, check the path is real: right clock, right period, no missing false path or multicycle intent. Next, read where the time goes. Here two multipliers in series take most of the 2 ns, so logic depth is the problem. Small misses can go to the tool: better cells, or restructuring. A miss in two chained multipliers usually needs an RTL change, such as a register between them.

Levels of logic count the gates on the longest path between two flops. Before placement there are no real wire delays, so the count is a quick and stable estimate. A team can set a budget, such as 20 levels at the target clock, and catch deep paths in RTL review.

Tools can upsize cells, restructure logic and buffer long wires, and that often closes small misses. They cannot change the cycle-level design: a register that is not in the RTL stays absent. When the miss is large or repeats after each tool run, an RTL change is cheaper than many tool runs.

The netlist no longer has one flop for each RTL flop. A normal RTL-to-netlist equivalence check matches flops one to one, so it reports a mismatch. You then need sequential equivalence, which compares only the outputs over time, and it is slower. Waveform debug also gets harder, because RTL register names no longer exist in the netlist.

Group the paths by start and end block and by cause. Often a few root causes explain most of them, such as one high-fanout signal, one bad constraint or one deep block. Fix the worst groups, then rerun and track WNS (the worst negative slack) and TNS (the sum of all negative slack).

An exception is legal only if the design already gives the path two cycles. The source must hold its value and the capture must happen every other cycle. If it does not, the exception hides a real bug from timing. Otherwise, weigh an RTL fix and its re-verification against physical fixes, or a spec change such as a lower clock. Write down who signed off the exception and why.

The exception is a promise that the source stays stable for two cycles before each capture. Only the RTL keeps that promise, and RTL changes later. So write an assertion: the source is stable at every capture edge. Simulation or formal tools then check the promise on every change.

A broad false path, such as one on all inputs, also removes paths that do matter. STA then reports them as unconstrained, not as failing. If nobody reads the unconstrained-endpoint list, the paths are never timed. Gate-level simulation without delays will not catch it either.

An RTL change fixes the cause but restarts verification and synthesis. A physical fix keeps the RTL frozen, but it may cost area, power or days of runs, and may not converge. A spec change may be cheapest if the system can absorb it. Examples are a lower clock or one more cycle of latency. The choice depends on margin, schedule and who owns each risk.

Keep every exception in one reviewed file, each with an owner, a reason and a proof such as an assertion. Block owners sign off their exceptions before integration. Run constraint checks on each release for unconstrained endpoints and overlapping exceptions. Re-review all exceptions when the RTL of their block changes.

It helps setup and hurts hold on the same capture flop. The late capture edge gives the long path 300 ps more time. But new data from the short path now has 300 ps longer to race in before the delayed edge. The run shows it: the long path is fixed, and the short path now changes inside the hold window.

Useful skew borrows time from the next stage, so it needs slack there and costs no latency. A pipeline register adds a whole cycle of time but changes the cycle count, so the RTL and its verification change. Skew is a physical-design fix; a register is an architectural one.

Around any loop of registers, the skews add up to zero. The time one stage gains, another stage in the loop loses. So the period is bounded below by the average stage delay around the loop. A single-register loop has zero skew to itself, so only faster logic helps.

Then the signs flip. The long path loses that much time for setup, and the hold check becomes easier by the same amount. It often happens when data flows against the direction the clock tree was built in.

Before CTS the clock is ideal, with the same arrival at every flop. The real tree has buffers, so some capture flops get their clock later than their launch flops. Short paths into those flops now fail hold. That is why hold repair runs after CTS, with propagated clocks.