Architecture Interview Questions

A data hazard (read after write) happens when an instruction needs a result that is still in the pipeline. A structural hazard is two instructions needing one resource, and a control hazard is a branch that changes which instructions follow. Forwarding sends a result from a later stage straight to the next instruction's EX input. That removes most data stalls, but a load followed by a use still costs one bubble.

An ALU result exists at the end of EX, just in time for the next instruction's EX. A load's data exists only at the end of MEM, one stage later. Forwarding cannot send data back in time, so the dependent instruction waits one cycle.

RAW: a read must see an earlier write. WAR: a later write must not land before an earlier read. WAW: two writes must land in program order. In a simple in-order pipeline, reads happen in ID and writes in WB, both in order, so only RAW occurs. WAR and WAW appear with out-of-order issue or units of different latency.

Each stage does less work, so the clock rises. But results take more stages to appear, so dependent instructions wait more cycles. Branches resolve later and flush more instructions, and forwarding paths multiply. Performance grows only if the clock gain beats the extra stall cycles, so measure it on real code.

The pipeline has already fetched the next instructions on the wrong path. When the branch resolves, they must be flushed, and each flushed slot is a lost cycle. Resolving earlier or predicting the branch cuts the penalty. A flushed instruction must never write a register or memory.

A 16-byte line needs 4 offset bits. 4 KB divided by 16 bytes is 256 lines, so 8 index bits. The other 20 bits are the tag. For 0x1234_5678: offset 8, index 0x67, tag 0x12345.

There are now 128 sets of two lines, so the index drops to 7 bits and the tag grows to 21. A lookup compares two tags in parallel and picks the matching way. On a miss, a replacement rule such as LRU (least recently used) chooses the victim. More ways cut conflict misses, but add comparators and a slower hit path.

A compulsory miss is the first touch of a line, which no cache avoids. A capacity miss happens when the working set is bigger than the cache. A conflict miss happens when lines that would fit compete for one set. More ways fix conflict misses; only a bigger cache fixes capacity misses.

Any address whose tag is 0 hits on an empty cache and returns garbage data. Each line needs a valid bit, cleared at reset and set when the line is filled. Clearing only the valid bits is cheaper than clearing a whole tag RAM.

Treat the cache as invisible: a reference model is just a flat memory, and every read must match it. At the end, flush the cache and compare the final memory images. Aim stimulus at aliasing addresses, evictions of dirty lines, and reads right after writes. Add assertions on internal rules, because a final-image mismatch is hard to trace back.

Write-through sends every store to memory, so memory always has the latest data, but traffic is high. Write-back updates only the cache and marks the line dirty, and memory is written when the line is evicted. That saves traffic, but memory can be stale. Any other reader of memory, such as a DMA engine, then needs coherence hardware or software cleaning.

Write-allocate fetches the line on a store miss and then writes into the cache. It helps when nearby data is used again soon. No-write-allocate sends the store straight to memory and leaves the cache alone. It suits streaming writes that are never read back. Write-back caches usually allocate; write-through caches often do not.

The dirty bit records that the line differs from memory. On eviction, a clean line can simply be dropped, while a dirty one must be written back first. Without the bit, the cache would write back every evicted line and lose much of its saving.

If the CPU still caches that line, it hits its own old copy and never sees the DMA data. Without coherence hardware, software must invalidate the line before reading. Before a DMA reads memory, software must clean dirty lines instead.

Both caches can hold the same line, and one CPU's write leaves the other's copy stale. A coherence protocol such as MESI tracks each line's state and snoops or invalidates the other copy. Verification runs both CPUs at once on the same lines, including different bytes of one line. A memory reference model then checks every read.

Instruction 2 reads r1, written two instructions earlier, so it needs the MEM/WB forwarding path. The design has only the EX/MEM path for distance 1, so it read the stale r1. The directed tests used only back-to-back dependencies. Coverage should cross the producer type with the distance, 1 to 3, for each source operand. Then an empty bin would have shown the missing case.

Each forwarding path serves one distance and one kind of producer. A load at distance 1 stalls, an ALU result at distance 2 uses MEM/WB, and distance 3 goes through the register file. Crossing type, distance and operand gives one bin per path. Then an untested path shows up as an empty bin.

The flushed instruction must not forward, and must not write the register file. If the forward select ignores the flush, the next correct instruction can take a wrong-path value. Test it by placing dependent instructions right after a mispredicted branch and right at an interrupt. Cover those as their own bins.

An ISS compare checks architectural results end to end, so it catches any wrong result. But it reports far from the cause. An assertion checks a local rule, such as "when EX reads the register MEM/WB is writing, the forward select picks MEM/WB". It fires at the cycle of the bug. Use both: the ISS for completeness, assertions to localize.

The plan comes first: every hazard, flush and exception case written as a coverage item. Sign-off needs those items closed, millions of random instructions with zero ISS mismatches, and assertions on the pipeline control that never fire. Formal proofs on the forwarding and stall logic help where tests are thin. Watch the bug-find rate fall to near zero over several weeks.

Latency in cycles goes up by one, because every result passes one more register. Throughput stays at one result per cycle, but each cycle can now be shorter. So results per second go up if the cut really shortens the slowest stage. The register also costs flops and power. The clock is set by the slowest stage, not the average.

The clock must fit the slowest stage. The products are still made in one stage, and one 8-bit multiplier is about 31 levels deep. The adder that moved out was short. To go faster, the cut has to go inside the multiplier itself.

Pipelining keeps one copy of the logic and adds registers, so it costs little area but adds latency. Two copies double the area and keep latency the same. But you need logic to split the work and merge the results in order. Pipelining needs the logic to be cut; parallel copies need the work to be independent.

The valid bit now arrives one cycle before its data. The next block accepts a result that is still the previous one, and the last result has no valid at all. Every control bit that describes the data must pass through the same number of registers.

Use a skid buffer: an output register plus one spare entry. in_ready is simply "the spare entry is empty", which is a flop. When the sink stalls, the beat already in flight lands in the spare entry. When the sink is ready again, the spare drains first. Two entries are needed, because ready reaches the source one cycle late.

When the sink drops ready, the stage only tells the source at the next edge. In that cycle the source may already send one more beat. The output register holds the stalled beat and the spare holds the one in flight. With one entry, the stage must stall every other cycle to stay safe.

Then up to two beats can be in flight when the sink stalls. The buffer needs room for all of them. In general, the spare space must cover the round-trip delay of the ready signal. This is the same arithmetic as a credit scheme or a FIFO almost-full threshold.

Both store two beats and both can drive ready from a flop. A skid buffer keeps the output register at the output, so out_data comes straight from a flop and needs no read mux. A FIFO has pointers and a read mux, which costs more logic. It scales to any depth with the same code.

Retiming moves registers through logic without changing what appears at the outputs, or when. Here the second register buys nothing, so move it back across the multiply. It must go on every path that crosses the cut: the sum and also c. The flop count stays at 34, and the measured depth drops from 42 to 31 levels.

The output combines values that entered together. If one input crosses one register fewer, it meets the other inputs a cycle early. Then the output mixes data from two different cycles. Counting registers on each input-to-output path is the check.

A loop has a fixed number of registers. Moving one more register into it makes the loop take two cycles to go round. The result is then two interleaved sums, not one. Speeding up a loop needs a different algorithm or a faster adder, not a moved register.

Yes. Two partial sums, one for even inputs and one for odd, each get two cycles for their adder. At the end, one more add combines them. This is a real technique, but it changes the design: an extra cycle and an extra adder at the end.

Pipelining adds registers, so latency grows and the rest of the system must accept it. Retiming only moves existing registers, so latency and the interface stay the same. Retiming is the first thing to try when a stage is badly balanced. Pipelining is for when every stage is already full.

Start with questions: is the limit the clock, the datapath width, or dependencies between packets? Then compare three options. A deeper pipeline adds latency and hazards. Two lanes double area and need ordering at the merge. A wider datapath processes two units per cycle, but needs alignment logic. Choose by area, power, latency budget and verification effort, and prototype the risky part first.

A wider datapath keeps one control path and one ordering, but packets rarely fill whole words. So it needs alignment and partial-word handling. Two lanes keep the narrow logic, but each lane needs control and the merge must restore order. Short packets favour lanes; long streaming data favours width.

A deeper pipeline adds hazard and stall scenarios, which need directed tests and coverage of back-to-back dependencies. Two lanes add ordering checks at the merge and tests that make the lanes finish out of order. A wider datapath adds alignment corners. Count that work in weeks and put it next to the area and power numbers.

Then a deeper pipeline creates a read-after-write hazard. The next packet may read the table before the earlier update has been written back. You need forwarding of the in-flight update, or a stall when the same entry is used. Both add logic and rare cases that the verification plan must cover.

The flop changes en_q just after the rising edge, while clk is still high. So the AND output rises in the middle of a high phase, and the gated flops see an extra edge. A clock-gating cell puts a latch in front of the AND. The latch is open while clk is low and holds while it is high. So the enable can only change the gated clock between pulses.

While the clock is low, the AND output is 0 whatever the enable does. So the enable may change freely then. When the clock rises, the latch closes and holds the enable for the whole high phase. The gated clock then shows either a full pulse or none.

The library cell carries setup and hold checks on its enable pin, so STA checks the enable against the clock. Clock-tree tools also know it is a gate in the clock path. Loose gates get none of that. Synthesis can insert the cell for you from ordinary enables, if the flow has a gating step and a library.

A gate near the root stops the most clock tree when the whole block is idle, but only then. Small gates near registers catch more idle cycles, but each costs a cell and timing on its enable. Decide from measured activity: which groups are idle together, and how often. Check the result with power analysis on realistic traffic.

In scan mode the flops must shift on every clock, whatever the functional enable says. So the scan version of the ICG cell has an extra scan-enable input, ORed with the enable. Test logic holds it high, so the gated clock runs.

An enable keeps the clock running. When en is low, an enabled flop or a feedback mux keeps the old value. The output holds, but every clock edge still reaches the flops. A gated clock stops the edges themselves, so the clock pins and that branch of the clock tree stop switching. Gating saves more power but needs an ICG cell and more care in timing.

Dynamic power grows with how often a node switches, its capacitance, the square of the supply and the frequency. The clock switches twice every cycle, more than any data signal. It also drives every flop's clock pin and a large buffered tree. So stopping it where it is not needed saves a lot.

If the RTL uses plain enables, a synthesis gating step can group flops that share an enable behind one library ICG. The RTL stays simple and simulates like any enabled register. Hand-placed gates give control, for example to gate a whole block from one signal, but must use the library cell.

With an enable flop, en is one more input to the D path, so it must meet the flop's setup time. With an ICG, en must meet the gate's own setup check before the clock rises. That check can be tighter, because the gate sits early in the clock tree. A late enable can stop you from gating.

First split the budget into dynamic power and leakage, measured on real use cases. Clock gating and operand isolation cut switching, and DVFS lowers voltage and frequency when the load allows. Multi-Vt cells and power gating cut leakage. Power gating needs isolation cells, retention for any state that must survive, and a controller to sequence them. Every step adds verification: UPF-aware simulation and low-power structural checks.

Stopping the clock removes dynamic power only. Transistors still leak while the supply is on. In small process nodes, leakage can be a large part of the total. Only removing the supply removes it, at the cost of losing state and a wake-up time.

For that cycle the domain's outputs are unknown, and always-on logic samples them. Power-down must go in order: isolate, save state into retention, then switch off. Power-up goes the other way: switch on, restore, then release isolation.

DVFS keeps the block running at a lower voltage and frequency, so it keeps its state and cuts dynamic power steeply. It suits work that can run slower. Power gating removes leakage completely, but loses state unless retained, and takes time to wake. It suits blocks that sit idle for long periods.

Write the intent in UPF: domains, supplies, power states, isolation and retention. Run simulation that reads the UPF, so off domains really corrupt their outputs, and test every power-state change. Add structural checks that isolation cells and level shifters sit where the states need them. Then check the netlist with its power cells against the RTL with low-power equivalence.

A register that needs retention but was left out of the retention list. In plain RTL it never loses its value, so wake-up looks perfect. In silicon it comes back random after power-up. Only power-aware simulation, which corrupts non-retained state at power-off, shows it.

Write the mux as y = s ? b : a and put one input on the select. NOT a is a ? 0 : 1. AND is a ? b : 0, and OR is a ? 1 : b. XOR is a ? ~b : b, so it needs a second mux to make ~b. Five muxes cover all four gates.

Four NANDs are enough. One NAND with its inputs tied makes ~s. Two NANDs gate a with ~s and b with s. A last NAND combines them, because NAND of two NANDs is an OR of two ANDs.

Drive the two inputs onto the select and tie the four data inputs to the truth table. The select then picks the output row directly. Changing the four constants changes the function, with no new wiring. This is how an FPGA look-up table works.

With constants it makes NOT and AND, and NOT plus AND can express every Boolean function. A mux also splits a function on one variable: f = x ? f(x=1) : f(x=0). Repeat the split on each variable and you get a tree of muxes for any truth table.

Name each state by the longest prefix of 1011 seen so far: none, 1, 10 and 101. In 101, an input of 1 completes the pattern, so match goes high. The next state is 1, because that last 1 can start the next pattern. An input of 0 in 101 goes to 10, not to the start. This Mealy version needs four states.

The Moore version needs a fifth state, "1011 seen", and match comes from that state alone. So it rises one cycle later, after the edge that enters the state. The Mealy output rises in the cycle of the last bit. But it can also glitch with the input.

In state 1, another 1 still leaves a 1 as the newest bit. So the machine must stay in S1. Going to S0 throws away a valid start, and 11011 never reaches S101.

Keep the last three bits and compare them, with the current bit, against 1011. Overlap needs no extra logic, because every window is checked. It costs one flop per pattern bit, while the FSM needs only enough flops to count its states. For long patterns, the FSM is smaller.

Register the signal once and compare old with new: rise = sig & ~sig_q. It is a detector for the sequence 01. The pulse lasts one clock. If sig comes from another clock domain, synchronize it first.

Use x != 0 && (x & (x - 1)) == 0. A power of two has exactly one bit set. Subtracting 1 clears that bit and sets all the bits below it, so the AND is zero. The x != 0 part matters, because zero also gives a zero AND. In hardware it is a subtractor, an AND and two zero checks.

-128 breaks it. Its pattern is 1000_0000, one bit set. In 8 bits, -128 - 1 wraps to 127, so the AND is zero. Check x > 0 instead of x != 0.

The loop looks at all 8 bits every time. The trick clears one 1 per step, so it takes as many steps as there are ones. In software, that saves time for sparse words. In hardware, the fixed 8-step loop unrolls to a popcount tree. The clear-lowest loop must be bounded to 8 steps before synthesis; it then gives similar logic, not fewer steps.

Subtracting 1 borrows from the lowest 1. That bit becomes 0 and every 0 below it becomes 1. Bits above it do not change. ANDing with x keeps the upper bits and zeroes the rest.

Binary to Gray is g = b ^ (b >> 1). The way back is not the same formula. Each binary bit is the XOR of all the Gray bits at and above it. Consecutive Gray values differ in one bit, including the wrap from 15 to 0.