Interview Question · Debug
Stale APB Read Data
The Question
The interviewer asks
A register read-back test fails only on the peripheral that adds wait states. Every read returns zero or the previous value. The writes look right on the waveform. Where do you look first?
Illustrative APB read excerpt
PSEL PENABLE PREADY PRDATA
1 0 0 0000
1 1 0 0000
1 1 1 1234
Monitor reported 0000; expected 1234You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
At the edge where the read data is taken. PRDATA needs to be valid only at the completion edge, where PSEL, PENABLE and PREADY are all high. So a sampler at the first ACCESS edge reads data that is not ready yet. Zero-wait peripherals hide the bug, because their first ACCESS edge is the completion edge. Capture only when PREADY is high too, and run every regression with wait states.
A token flies to a monitor at the edge where it publishes a transfer.
- Cycle 0
Setup of the read of 0x100. The early monitor publishes now, with PRDATA still 0 from before: the completer has not answered yet.
- Cycle 2
The completion edge: PSEL, PENABLE and PREADY are all 1. The monitor publishes the read with 5a, the value the completer drove for this transfer.
- Cycle 3
Setup of the read of 0x110. The early monitor publishes again, with 5a: the data of the previous read, still on PRDATA.
- Cycle 5
Completion: the monitor publishes 41504234, the ID register.
- Cycle 6
Setup of the write to 0x118. The early monitor publishes it as OKAY; nothing about the response is known yet.
- Cycle 8
Completion with PSLVERR: 0x118 is unmapped. Only the monitor that waited sees the error.
Measured. A sampler that reads PRDATA before the completion edge gets 0, then the previous read's value. That is the bug's symptom.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer goes straight to the edge where read data is taken and names PSEL && PENABLE && PREADY. It explains why peripherals with no wait states pass.
What Interviewers Listen For (Mid-Level)
A good mid-level answer also checks the completer. A completer whose PRDATA comes a cycle late gives the same symptom with a correct sampler. So it reads the waveform at the completion edge before blaming either side, then adds wait-state coverage.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
What IfProve ItBreak ItScale It
- Stale APB Read Data
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What IfWhat Holds During APB Wait StatesL1 JuniorL2 Mid-Level
The completer holds PREADY low for three cycles. What is the requester allowed to change during those cycles?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Nothing it set in SETUP: PADDR, PWRITE, PSEL, PENABLE and PPROT stay unchanged. So do PWDATA and PSTRB for a write, and any user request signals. The hold lasts from the SETUP-to-ACCESS transition until PREADY is high. The only free signal in that window is the completer's own PREADY. Any number of wait states is legal, from zero upwards.
The Address That Moved in a Wait StateA write to 0x1c with two wait states; PADDR moves to 0x20 in the second one. Then two reads. All cyclesA token flies at each completion edge: the write data to the completer, the read data back.
- Cycle 0
Setup of the write: PSEL high, PENABLE low, PADDR = 0x1c, PWDATA = 0x66. From here to the completion edge every one of these must stay put.
- Cycle 2
The second access cycle, still waiting: PADDR is now 0x20. The property
stable_ctlfails at this edge, and the procedural checker prints stable at the same edge. - Cycle 3
PREADY is 1: the completion edge. The completer acts on what it sees now, so 0x66 lands at 0x20.
- Cycle 5
The read of 0x1c returns 0x00. The data was never written there.
- Cycle 7
The read of 0x20 returns 0x66: the neighbour took the write.
Measured on the lesson bench. PADDR moved during a wait state, so the write of 0x66 landed at 0x20, not 0x1c.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer lists the signals that must hold. It says the hold starts when SETUP moves to ACCESS, not at the first wait cycle.
What Interviewers Listen For (Mid-Level)
A good mid-level answer writes the stability property, such as
psel && penable && !pready |=> $stable(paddr) && $stable(pwrite) && penable. It knows PWDATA only matters for writes. - Cycle 0
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Break ItA Completer That Never AnswersL2 Mid-LevelL3 Senior
A completer holds PREADY low forever. Is that an APB protocol violation? How does your bench catch it?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
It is not a protocol violation, because APB allows any number of wait states. "Too long" is a system property, so a protocol checker cannot call it wrong. The bench uses a watchdog instead, with a limit taken from the peripheral's documented maximum. The watchdog reports a hang when the wait reaches that limit. In formal, the same requirement is a bounded response property, or a liveness property with fairness assumptions on the completer's inputs.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer says the APB spec allows waits of any length. It puts the time limit in a separate watchdog, not in the protocol checker.
What Interviewers Listen For (Senior)
A good senior answer takes the limit for each completer from its documentation and makes it a parameter. It asks what the system does about a hang, for example a bridge timeout that returns an error.
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Scale ItTimeouts in an APB BridgeL3 SeniorL4 Staff
A completer hangs with PREADY low. Should the bridge time out? What does it return, and what is the risk?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
A timeout is system policy, not protocol. After a programmed limit, the bridge returns SLVERR so the CPU is not stuck forever. The risk is on the APB side: the requester must hold the transfer until PREADY, so the bridge cannot legally abandon it. It either keeps that segment blocked and fails every later access, or resets the completer. Specify which, raise an interrupt, and verify that recovery path.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Senior)
A good senior answer separates the AXI response from the stuck APB transfer. It knows the bridge cannot simply drop an APB access that has started.
What Interviewers Listen For (Staff)
A good staff answer makes it an architecture decision. It decides where timeouts live, how a hung peripheral is reset, and how software finds out. It adds an error-injection test to the verification plan.
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Break ItA Completer That Never AnswersL2 Mid-LevelL3 Senior
A completer holds PREADY low forever. Is that an APB protocol violation? How does your bench catch it?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
It is not a protocol violation, because APB allows any number of wait states. "Too long" is a system property, so a protocol checker cannot call it wrong. The bench uses a watchdog instead, with a limit taken from the peripheral's documented maximum. The watchdog reports a hang when the wait reaches that limit. In formal, the same requirement is a bounded response property, or a liveness property with fairness assumptions on the completer's inputs.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer says the APB spec allows waits of any length. It puts the time limit in a separate watchdog, not in the protocol checker.
What Interviewers Listen For (Senior)
A good senior answer takes the limit for each completer from its documentation and makes it a parameter. It asks what the system does about a hang, for example a bridge timeout that returns an error.
-
Scale ItTimeouts in an APB BridgeL3 SeniorL4 Staff
A completer hangs with PREADY low. Should the bridge time out? What does it return, and what is the risk?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
A timeout is system policy, not protocol. After a programmed limit, the bridge returns SLVERR so the CPU is not stuck forever. The risk is on the APB side: the requester must hold the transfer until PREADY, so the bridge cannot legally abandon it. It either keeps that segment blocked and fails every later access, or resets the completer. Specify which, raise an interrupt, and verify that recovery path.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Senior)
A good senior answer separates the AXI response from the stuck APB transfer. It knows the bridge cannot simply drop an APB access that has started.
What Interviewers Listen For (Staff)
A good staff answer makes it an architecture decision. It decides where timeouts live, how a hung peripheral is reset, and how software finds out. It adds an error-injection test to the verification plan.
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Scale ItDesigning the APB MonitorL2 Mid-LevelL3 Senior
Design the monitor of an APB agent. When does it publish a transfer, and what goes in the item?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
It publishes once per transfer, at the edge where PSEL, PENABLE and PREADY are all high. Only then are PRDATA and PSLVERR valid. The item carries the address, direction, PPROT, PWDATA and PSTRB, all stable since SETUP. It also carries PRDATA or the error at completion, and the wait count: the ACCESS cycles with PREADY low. Sampling through a clocking block keeps the monitor free of races with the DUT.
A Write and a Read with Two Wait States EachThe completer holds PREADY low for two access cycles in every transfer. All cyclesThe bridge is ringed while the completer holds PREADY low.
- Cycle 3
Setup of the write of 0xbeef.
- Cycle 4
Access,
PREADY= 0: the first wait state. Every signal the bridge drives keeps its value. - Cycle 6
Second wait state over:
PREADY= 1 and the write completes. One transfer, four edges. - Cycle 8
The read's data is on
PRDATAalready, butPREADYis 0. The bridge must not take it yet. - Cycle 10
The read completes and the bridge takes 0xbeef here, at the only edge that counts.
Measured with two wait states per transfer. The monitor takes PRDATA only at the completion edge and counts the waits.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer publishes at completion, not when PSEL rises, and counts wait cycles. It knows a monitor that reports at PSEL rise logs stale PRDATA from SETUP and shows no waits.
What Interviewers Listen For (Senior)
A good senior answer keeps protocol checks out of the monitor, in a separate checker or assertions. It adds coverage on wait count, back-to-back transfers and errors. One monitor port feeds both the scoreboard and the register model predictor.
- Cycle 3
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Break ItWhat an APB Checker Cannot SeeL2 Mid-LevelL3 Senior
Your APB protocol checker passes on every test. Which completer bugs can still be in the design?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Every bug that keeps the wires legal can remain, because a wire checker only proves the protocol. A completer that acts in every selected cycle still obeys the handshake. So does one that returns read data one transfer late, ignores PSTRB, acts without its PSEL, or raises PSLVERR a cycle early. A register model or scoreboard that predicts data and responses catches the rest. But it needs traffic with wait states, back-to-back transfers, sparse strobes and errors.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer separates checking the rules on the wires from checking the data. It names at least three bugs that keep the wires legal.
What Interviewers Listen For (Senior)
A good senior answer turns the list into a test plan. Each bug gets the stimulus it needs, such as waits, partial strobes or two completers, plus a coverage point. Only then does a pass mean something.
Missed Corner
If the APB property module and the register read-back both pass, the completer is correct.
A full-word write to RAM with zero wait states makes faulty completers look the same as a good one. Without wait states, partial strobes and error cases, the scoreboard never sees the difference.
Source Lesson P3.10 and problem P3.10.2 (six faulty completers behave like the correct block under full-word zero-wait writes)
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Prove ItSolve P3.10.2: Break the CompletersSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
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Prove ItSolve P3.9.1: The APB MonitorSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
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Prove ItSolve P3.3.1: Stale Read DataSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Missed Corner
Sampling PRDATA at the first ACCESS edge is safe: the completer had the whole SETUP cycle to prepare it.
With wait states, the first ACCESS edge is not the end of the transfer. PRDATA need not be valid until the transfer ends. The sampler below reads 00000000 where the completion edge carries c0de0000.
Run It
FAIL naive sampler (first access edge): 00000000 PASS correct sampler (PSEL&PENABLE&PREADY): c0de0000Misconception
The completer is broken because PRDATA changes during the wait states.
PRDATA has no validity requirement before the completion cycle. It may hold anything, and change freely, while PREADY is low.
Source AMBA APB Protocol Specification IHI 0024E §A.1 Validity rules
Half-Truth
Fix it by sampling one cycle later.
That fixes exactly one wait state. APB allows any number of wait states. So the only correct capture point is the edge with PREADY high.