SPI Interview Questions

CPOL is the clock's idle level. CPHA picks the sampling edge. CPHA 0 samples on the first edge after the clock leaves idle; CPHA 1 samples on the second. The other edge launches the next bit. So modes 0 (CPOL 0, CPHA 0) and 3 (1, 1) sample on rising edges, and modes 1 and 2 on falling edges. With CPHA 0, the first bit must already be on the line when CS falls.

At the falling edge of CS. With CPHA 0 there is no launch edge before the first sample. So both sides put bit 7 out as soon as they are selected. They launch every later bit on the trailing edge. A peripheral that waits for a clock edge to drive bit 7 delivers the byte one bit late.

Only the clock level while idle, at the CS edges: low in mode 0, high in mode 3. In both, the flash latches input on rising edges and drives output on falling edges. So data transfer is identical. It matters at the frame boundary: the controller must hold the idle clock level when it moves CS. The CS-to-clock setup and hold times still apply.

A clean one-bit shift is the signature of an SPI mode mismatch, not noise. Both sides move one bit per clock but disagree on which edge carries it. The controller samples each bit just before the peripheral launches it, so it gets the previous bit. The lost bit turns up in the next byte. With a mode-0 controller and a mode-1 peripheral, writes can still pass. But their only hold time is the launch delay.

Both sides still move one bit per clock and agree on the number of clocks. They disagree only on which of the two edges in a clock period carries the bit. Those edges are half a period apart. Sampling on the launch edge reads the value from before the launch, which is the previous bit. So every bit lands exactly one place late.

On the shared edge, the only hold time is the launching side's clock-to-output delay. So a model with no delays always takes the old bit and looks correct. In silicon, hold must beat the receiver's requirement, such as tCHDX of 2 ns on the W25Q128JV. For same-cycle reads, start from half a clock period. Subtract the peripheral's clock-to-output time (tCLQV) and the controller's input setup; the rest is the setup margin.

From configuration, never by guessing: rising when CPOL equals CPHA, falling otherwise. A monitor that infers the mode can be fooled by the very mismatch it should catch. On the wires alone, a checker can assert the idle clock level at CS edges and MISO released while deselected. It can also check stable data on the sample edge, whole bytes on writes and CS-to-clock times. Whether the bytes are right needs a reference model.

Use a wire monitor for every supported mode and lane width. Add wire checks that need no data: idle level, MISO and IO release, CS timing and whole bytes on writes. A strict flash model refuses what the datasheet forbids: programs without WEL, quad reads with QE clear, commands while BUSY. A scoreboard compares readback with a reference memory. Bugs escape through a lenient model, page-wrap writes, off-by-one dummy counts and turnaround timing.

Plant one fault per class, such as a missing WEL, a late IO release or a page-wrap error. Run every test against every fault and record which check fires. A fault with no mark is a hole, so add a program for it. On the lesson bench the wire checker caught 1 fault of 11, and readbacks caught the rest.

A deselected peripheral must put MISO in high impedance, so only the selected one drives it. The W25Q128JV floats its outputs whenever /CS is high. If a deselected device keeps driving, two outputs fight. Simulation shows x on the bits where they disagree. A board shows mid-rail levels, wrong bits and extra current. Clock, MOSI and MISO are shared; each device has its own active-low select.

Separate selects cost one pin per device, but let you talk to any device alone, at its own mode and length. A daisy chain uses one select, and each device's output feeds the next device's input. So the chain is one long shift register, and every update shifts through every device. One broken device breaks the chain, and every device must support pass-through. It suits strings of identical parts, such as LED drivers or shift registers.

The first device needs its output-disable time to let go of MISO: 7 ns maximum (tSHQZ) on the W25Q128JV. The next device's first driven bit must come later than that. The same device also has its own minimum deselect time before it accepts a new command. On that flash it is 10 ns after a read and 50 ns after a program, erase or write.

The controller sends EBh on IO0 alone for 8 clocks. Then it sends the 24-bit address on all four lanes in 6 clocks, and the mode byte in 2 more. Then come 4 dummy clocks, in which the controller must release the lanes. From clock 20 the flash drives one byte every 2 clocks, high nibble first, with the top bit on IO3. QE in status register 2 must be set, because IO2 and IO3 replace the /WP and /HOLD pins.

The flash needs time to fetch the first byte after the last address bit. Read Data (03h) gets that time by running slowly: on the W25Q128JV it is limited to 50 MHz. Fast Read (0Bh) adds eight dummy clocks so the whole frame can run at the full rated clock. That is 133 MHz in the 3.0 to 3.6 V range. The quad I/O read sends the mode byte and then only four dummy clocks.

The flash drives data only after its eighth dummy clock. The controller starts sampling two clocks early, so it reads two junk bits first. Every byte it returns is then shifted by two bits. Check the dummy count per command, because the quad reads use different counts.

Both drivers are on during the first data clock. Simulation shows x on lanes where they disagree; the board shows mid-rail levels and wrong bits. A bench catches it with a wire rule: no lane has two drivers. Or it checks that the controller's output enables are off before the first data clock. Waiting for a data mismatch is not enough, because matching bits hide the fight.

One EBh read of the line: 8 instruction, 6 address, 2 mode, 4 dummy and 64 data clocks, 84 in all. Burst wrap, set with 77h, does not reduce that. It starts at the byte that missed and wraps within the aligned section. So the CPU can resume while the rest of the line streams in.

Page Program writes within one 256-byte page. The low address byte wraps inside the page, so bytes 256 to 299 overwrite bytes 0 to 43. The next page is never touched. The driver must split writes at page boundaries. It must send Write Enable (06h) before every program, because WEL clears when a program finishes. It must also raise CS only after a whole byte, and poll BUSY before the next command.

Write Enable (06h) sets WEL, a guard against stray writes. The flash clears it after every program, erase or status write, so each one needs a fresh 06h. After CS rises, the operation runs on its own for milliseconds. Firmware polls status register 1 with 05h until BUSY, bit 0, reads 0. While BUSY, the flash ignores everything except status reads and suspend.

The model shared the driver's wrong belief, a linear address. So the two agreed, and the test checked nothing the datasheet says. Fix the model first: feed it stimulus the datasheet forbids or defines unusually, and expect the datasheet's result. Examples are a program past a page, a program without 06h and a quad read with QE clear. Then cover page offset × length, including lengths that cross the boundary.

The datasheet defines Page Program only on erased locations, which read FFh. So the result is not something to rely on. In practice, programming can only clear bits, never set them. To get 1s back you must erase, and the smallest erase on this flash is a 4 KB sector. So updating one byte means a read, a sector erase and a reprogram.