UART Interview Questions

Idle is 1. The frame starts with a 0 start bit. Then come the eight data bits, least significant bit first, and a 1 stop bit. For A5h that is 0, then 1 0 1 0 0 1 0 1, then 1: ten bit-times. Even parity adds one bit before the stop bit, chosen so the count of 1s is even. A5h already has four 1s, so the parity bit is 0 and the frame takes eleven bit-times.

There is no clock wire, so the receiver needs one moment it agrees on with the transmitter. That moment is the high-to-low edge of the start bit. The receiver times every bit from that edge. The stop bit returns the line high. So the next frame always begins with a fresh falling edge, even when the last data bit was 0.

SPI sends the clock, so the receiver samples on an edge it is given, and the rate can change freely. A UART receiver must rebuild bit timing from the start edge and its own clock. So both ends must agree closely on the baud rate. Frames also carry start and stop overhead: 8N1 moves 8 data bits in 10 bit-times. The gain is fewer wires and no shared clock across a cable.

It catches any odd number of flipped bits in the data and parity bits. It passes any even number. So a burst that flips two adjacent bits passes. Parity also says nothing about a lost or extra frame. Systems that care add a checksum or CRC at the packet level, above the UART.

Parity stores one fact: whether the count of ones is even or odd. Flipping one bit changes that count by one, so the parity no longer matches. Flipping two bits changes the count by two or by zero, so it still matches. Any even number of flips cancels the same way.

There is no clock on the wire, so a fast local clock finds the start edge to within one tick. It then counts to the middle of every bit. A typical receiver rejects glitches in the middle of the start bit. There, 8 ticks after the edge, the line must still be low. After that it samples every 16 ticks, often with a 2-of-3 vote over ticks. At 16x a sample is off by at most a sixteenth of a bit; at 2x, by half a bit.

The ratio sets the quantisation error of finding the start edge: up to one tick, or 1/N of a bit. At 2x that is half a bit, which already uses the whole budget; at 16x it is about 6 %. Beyond that, the rate mismatch between the two clocks dominates. So 64x buys little and costs a faster clock and wider counters. Sixteen also leaves room for a centred vote over several ticks.

Two low ticks on two of the three vote ticks of one sample win the vote. One tick never does. The bench must time the glitch against the receiver's own sample ticks. A random glitch time rarely lands on two vote ticks, so the bench must know or sweep the sample position. The P6.5 bench did this and turned 55h into 45h with no flag.

Drift is zero at each start edge and grows with every bit. So the last sample, the stop bit, fails first. A receiver that samples exact bit centres has half a bit of slack over the nine bits before the stop. That is about ±5.6 %, shared by both ends. Real receivers do worse: the site's bench receiver first loses 8N1 frames at +4.5 % and −6 %. The 8E1 format fails earlier, because parity puts the stop bit one bit later.

The start edge is the only moment both ends agree on, and drift is zero there. Each later bit adds the same timing error. So the sample furthest from the start edge, the stop sample, has drifted most. This is also why the receiver restarts its count on every start edge. The error never carries from one frame to the next.

It helps only on the fast side, and only when frames stream back to back. There, with a fast transmitter, the stop sample comes late and can land in the next start bit. It then reads 0. A second stop bit puts idle time there instead. With idle time between frames it buys nothing: the P6.4 sweep shows 8N1 and 8N2 failing at the same steps.

Add up the error sources: this end's divisor rounding and clock tolerance, and the peer's oscillator tolerance over temperature and voltage. Compare the sum, in both directions, with the receiver's measured budget for the frame format in use, not a quoted 5 %. In simulation, sweep the peer rate in fine steps, both ways, in every supported format. Run frames back to back and with gaps. Record the first failing step as the sign-off number.

A rate error moves each sample further from its bit centre, and the stop bit moves most. The total room is about half a bit over the frame. A receiver that samples a little before the centre has less room on one side and more on the other. So quote the budget with its receiver, format and pacing.

A clean wire with lost bytes points inside the receiver, to an overrun. A frame completes before software read the previous byte, and the new byte overwrites it. Framing errors (the stop sample reads 0) and parity errors are visible on the wire; an overrun is not. A break is the line held low for longer than a whole frame. A correct receiver reports it once and delivers no byte. It hunts for a start only after the line is high again.

During a break the line is a continuous 0. A receiver that re-arms at once takes the low level as a new start every frame time. It delivers a stream of 00h framing errors. Waiting for the high level means the next frame begins on a real falling edge. A common bug that tests miss is a lost first frame after recovery: the receiver re-armed too late or too early.

The transmitter may send the next start bit soon after the line goes high. A receiver that waits a whole frame misses that falling edge. It loses the first byte, or starts in the middle of it and reads garbage. Re-arm on the first high level, then hunt for the next falling edge.

Each side drives RTS from its own receive FIFO level. The peer sees it as CTS and starts no new frame while CTS is deasserted. But frames already started, or already loaded in the transmitter, still arrive after RTS changes. So the trigger sits below full, and the room above it absorbs those frames. The P6.6 bench uses 12 of 16; a trigger at 16 left no room.

A flag is a bug only if it disagrees with what was sent. So the checker predicts flags from the stimulus. An injected short stop expects FE, a break expects one break and no byte, and a slow read expects overrun. It flags both a missing expected flag and an unexpected one. Banning all errors makes error tests impossible; ignoring flags misses a receiver that never sets them.

I use three independent parts. A wire monitor reports each frame after its stop sample. A reference model predicts bytes and flags from the stimulus and the read timing, and a scoreboard compares them. Stimulus sweeps the divisor and the peer rate error both ways, in every format, back to back and with gaps. It injects faults: parity, short stop, break, glitches, slow reads and CTS toggling. Before trusting the checker, I run it against a bank of known-faulty receivers.

After the stop sample. Until then there is no frame. The stop bit decides between a byte, a framing error and a break, and a break never gives a byte. A monitor that publishes at data bit 7 hands the scoreboard bytes that later turn out to be breaks or errors.

Run it against a bank of deliberately faulty receivers. Examples are a missing overrun flag, an off-centre sample, a one-tick start check and a broken break recovery. Add a legal variation, such as a rate error inside the budget. Every fault must make some check fire, and the legal case must stay silent. A fault that no test catches names the next test to write.

Rate tolerance worse than claimed: only a sweep to the first failing step catches it. A missing overrun flag: caught only when software reads slowly. The first frame lost after a break: caught by sending a frame right after recovery. An RTS trigger off by one: caught by filling the FIFO to exactly the trigger. Each needs a deliberate scenario; random traffic at the nominal rate rarely hits them.